Nonvolatile Storage Device Layer Selection Transistors
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Solution Overview
Problem
Existing nonvolatile storage devices with laminated memory layers face challenges in efficiently connecting to peripheral circuits due to the increased number of contacts and wirings, limiting the scalability and integration of such devices.
Innovation Solution
The implementation of layer selection transistors that connect to both first and second wirings of each unit memory layer, allowing for collective selection in the same plane, thereby reducing the number of bit lines drawn out and enabling increased laminations without modifying the peripheral circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of laminated memory layers is increased to achieve high storage density, then the storage capacity is improved, but the number of contacts and wirings connecting to peripheral circuits increases, making the draw-out extremely difficult
Solution Approach 1:
The bit lines are segmented into layer-specific bit lines (first bit lines for first memory layer, second bit lines for second memory layer) that are independently controlled by layer selection transistors. This segmentation allows each memory layer to be accessed through dedicated bit lines, preventing the need to draw out all bit lines from all layers to peripheral circuits, thus reducing wiring complexity while maintaining high storage density through multiple laminated layers
Solution Approach 2:
Layer selection transistors are introduced as intermediary elements between the laminated memory layers and the peripheral circuits. These transistors selectively connect specific memory layers to the bit lines, acting as mediators that control which layer is accessed. This intermediary structure enables independent control of each memory layer and simplifies the connection to peripheral circuits, as only the necessary bit lines need to be drawn out rather than all bit lines from all layers
2Reliability
If independent control of word lines and bit lines is implemented in phase change memory elements, then element characteristics are improved, but the number of contacts and wirings increases as the number of laminated memory layers increases
Solution Approach 1:
The bit line control is segmented by introducing layer selection transistors that independently control bit lines for each memory layer. This segmentation maintains the independent control capability necessary for reliable phase change memory operation while organizing the wiring structure so that each layer's bit lines are controlled separately, reducing the overall wiring complexity compared to a fully independent control scheme across all layers
Solution Approach 2:
The layer selection transistors provide multi-functional control by managing both the selection of memory layers and the control of bit lines. This universal control mechanism allows the same transistor structure to handle independent control requirements for multiple layers, reducing the total number of separate control elements needed while maintaining reliable element characteristics
Data Source
AI summary
A nonvolatile storage device having a plurality of unit memory layers, and a plurality of layer selection transistors is provided. The plurality of unit memory layers are laminated in a direction perpendicular to a layer surface of the unit memory layers. Each of the unit memory layers includes a plurality of first wirings, a plurality of second wirings provided non-parallel to the plurality of first wirings, and a recording layer provided between the plurality of first wirings and the plurality of second wirings. The plurality of layer selection transistors are connected to at least one of the plurality of first wirings and the plurality of second wirings of each of the unit memory layers, and collectively selects the at least one in the same plane.