Non-Volatile Storage Offloading Through Peer-to-Peer Device Commands
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Solution Overview
Problem
Conventional non-volatile memory devices lack direct addressability and autonomy, leading to increased CPU workload and data path bottlenecks in managing multiple devices, especially in systems with RAID protection schemes.
Innovation Solution
Implementing Controller Memory Buffer (CMB), Subsystem Level Memory (SLM), or Persistent Memory Region (PMR) to allow non-volatile memory devices to be directly addressable by the host, enabling peer-to-peer communication and reducing CPU involvement through device context information and peer commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If conventional non-volatile memory devices are used without direct addressability, then device autonomy is reduced, but CPU workload increases
Solution Approach 1:
The patent enables non-volatile memory devices to autonomously manage data distribution across RAID groups by implementing peer-to-peer communication protocols. Devices can independently generate peer commands to transfer data between themselves without CPU intervention, allowing each device to serve itself in data management operations while reducing the CPU's burden in coordinating these operations
2Productivity
If CPU manages data transfer between multiple non-volatile memory devices, then device coordination is achieved, but data path bottlenecks increase
Solution Approach 1:
The patent extracts the data transfer coordination function from the CPU by enabling direct peer-to-peer communication between non-volatile memory devices. The PCIe root complex is bypassed for intra-RAID data transfers, with devices communicating directly through dedicated peer command interfaces. This extraction of the coordination function from the CPU eliminates the data path bottleneck that would otherwise exist at the root complex level
3Productivity
If non-volatile memory devices lack direct addressability, then system simplicity is maintained, but system efficiency decreases
Solution Approach 1:
The patent implements a universal peer-to-peer communication interface that allows non-volatile memory devices to function both as data storage units and as autonomous communication nodes. The same PCIe bus infrastructure serves dual purposes: traditional CPU-controlled data transfers and direct peer-to-peer device communication. This multi-functionality enables direct addressability without requiring separate dedicated communication channels, thereby improving system efficiency while avoiding excessive infrastructure complexity
Data Source
AI summary
Various implementations relate to receiving, by a first non-volatile memory device from a host, a host command including device context information of a plurality of non-volatile memory devices. The device context includes an address of a buffer of each of the plurality of non-volatile memory devices, in response to receiving the host command. The first non-volatile memory device divides portions of host data corresponding to the host command among the plurality of non-volatile memory devices. The first non-volatile memory device sends to the host a transfer request indicating transfer of each of the portions of the host data to a respective one of the plurality of non-volatile memory devices. The first non-volatile memory device sends to each of the plurality of non-volatile memory devices other than the first non-volatile memory device, a peer command based on the device context information.