Nonvolatile Semiconductor Storage Device Self-Aligned Conductive Layer
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Solution Overview
Problem
Existing nonvolatile semiconductor storage devices face challenges in preventing the generation of voids and reducing wiring resistance, which affects the performance and efficiency of memory cells.
Innovation Solution
A method for manufacturing nonvolatile semiconductor storage devices involves forming a conductive layer self-aligned on a wiring layer, followed by annealing and stacking films into a stripe structure, which prevents void generation and enhances adhesion, thereby reducing wiring resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional manufacturing methods are used to form conductive layers and wiring structures, then the manufacturing process is simpler, but voids are generated between conductive layers and selector elements, leading to poor adhesion and high wiring resistance
Solution Approach 1:
The patent applies preliminary action by forming the conductive layer self-aligned on the wiring layer before stacking the memory cell stack. This preliminary positioning ensures proper alignment and contact between conductive layers and selector elements, preventing void formation and improving adhesion before the actual stacking process begins.
Solution Approach 2:
The patent introduces an intermediate annealing process between forming the conductive layer and stacking the memory cell stack. This annealing step acts as an intermediary that enhances adhesion and prevents void formation by treating the interface between conductive layers and selector elements, thereby improving reliability without significantly complicating the manufacturing process.
2Reliability
If conventional wiring structures are used, then the manufacturing process is simpler, but wiring resistance is high, affecting memory cell performance
Solution Approach 1:
The conductive layer is formed self-aligned on the wiring layer in advance, ensuring optimal positioning and contact area before the memory cell stack is stacked. This preliminary action reduces wiring resistance by ensuring good electrical contact without requiring complex wiring redesign.
Solution Approach 2:
The patent applies parameter changes by performing annealing treatment on the conductive layer, which changes the physical and electrical properties of the material. This annealing process reduces wiring resistance by improving the crystalline structure and electrical conductivity of the conductive layer, thereby enhancing memory cell performance without increasing structural complexity.
3Manufacturing precision
If conductive layers are formed without self-alignment, then the manufacturing process is simpler, but voids are generated between conductive layers and selector elements
Solution Approach 1:
The conductive layer is formed with self-alignment on the wiring layer, meaning the conductive layer automatically positions itself correctly relative to the wiring layer without requiring additional alignment steps. This self-service approach achieves high alignment precision while keeping the manufacturing process relatively simple, preventing void formation between conductive layers and selector elements.
4Reliability
If annealing is not performed on conductive layers, then the manufacturing process is simpler, but adhesion between conductive layers and selector elements is poor
Solution Approach 1:
Annealing is performed on the conductive layer as a preliminary step before stacking the memory cell stack. This preliminary annealing treatment enhances adhesion between conductive layers and selector elements by improving the material properties at the interface, ensuring strong bonding before the actual stacking process begins.
Solution Approach 2:
The annealing process changes the thermal and structural parameters of the conductive layer, improving its adhesion properties. By controlling the temperature and duration of the annealing process, the patent achieves strong adhesion between conductive layers and selector elements while managing energy consumption efficiently.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents voids between conductive layers and selector elements, improving adhesion and reducing wiring resistance, leading to enhanced performance and efficiency of memory cells.
Implementation Method 1
forming a first conductive layer self-aligned on a first wiring layer, and performing an annealing processing
Data Source
AI summary
A method for manufacturing a nonvolatile semiconductor storage device includes: forming a first conductive layer by self-alignment on a first wiring layer, and performing an annealing processing; stacking a first stacked film on the first conductive layer; processing the first stacked film, the first conductive layer, and the first wiring layer into a stripe structure extending in a first direction; forming and planarizing a first interlayer insulating film; forming a second wiring layer; forming a second conductive layer by self-alignment on the second wiring layer, and performing an annealing processing; processing the second wiring layer and the second conductive layer into a stripe structure extending in a second direction intersecting the first direction; and processing the first stacked film and the first interlayer insulating film below and between the second wiring layer, and forming a first memory cell having the first stacked film in a columnar shape.