Nonvolatile Semiconductor Storage Device Threshold Voltage Control
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Solution Overview
Problem
Conventional stacked NAND-type flash memory devices face challenges in precisely adjusting the threshold voltage of select transistors due to broad threshold voltage distribution, which affects the performance and bit density of nonvolatile semiconductor storage devices.
Innovation Solution
The proposed nonvolatile semiconductor storage device includes a memory string with multiple drain-side select transistors that can adjust their threshold voltage during write operations, utilizing a control circuit to manage bit lines and select gate lines, allowing for precise voltage control and threshold voltage adjustment through a series of voltage applications and bit line configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacked memory cells are used to increase bit density, then storage capacity is improved, but the threshold voltage distribution of select transistors becomes broader and harder to control
Solution Approach 1:
The patent applies preliminary action by performing threshold voltage adjustment operations on select transistors before they are fully integrated into the stacked memory structure. The control circuit executes write operations to adjust the threshold voltage of drain-side select transistors in advance, ensuring proper voltage distribution characteristics are established during manufacturing rather than attempting to correct deviations after device fabrication.
Solution Approach 2:
The patent employs parameter changes by dynamically adjusting the threshold voltage parameter of select transistors through controlled write operations. The control circuit applies different voltage levels (first voltage to write bit lines, second voltage to inhibit bit lines) to modify the threshold voltage distribution of drain-side select transistors, transforming the electrical characteristics to achieve narrower voltage distribution and improved control precision.
2Device complexity
If select transistor threshold voltage is not sufficiently adjusted, then device structure remains simple, but performance control capability is insufficient
Solution Approach 1:
The patent applies universality by designing the control circuit to perform multiple functions: it controls the threshold voltage adjustment of drain-side select transistors during write operations, manages the voltage application to bit lines and gate lines, and coordinates the entire threshold voltage tuning process. This multi-functional control approach achieves reliable performance control without proportionally increasing circuit complexity.
Solution Approach 2:
The patent implements feedback mechanisms where the control circuit monitors the threshold voltage distribution of select transistors and adjusts write operation parameters accordingly. The system uses verify operations to check whether threshold voltage adjustment has achieved the desired effect, and repeats write operations if necessary, creating a closed-loop feedback system that ensures reliable performance control.
3Ease of operation
If conventional write operations are used without bit line configuration, then operation is simple, but threshold voltage adjustment precision is insufficient
Solution Approach 1:
The patent applies segmentation by dividing the bit lines into different functional groups: write bit lines and inhibit bit lines. The control circuit segments the write operation into distinct phases where write bit lines receive the first voltage while inhibit bit lines receive the second voltage, enabling precise control over which transistors undergo threshold voltage adjustment and which remain unaffected.
Solution Approach 2:
The patent employs dynamics by making the bit line voltage application dynamic rather than static. The control circuit dynamically switches between different voltage levels for write and inhibit bit lines during the write operation, allowing the system to adaptively control the threshold voltage adjustment process and achieve higher precision through time-varying voltage application.
Data Source
AI summary
A control circuit for a nonvolatile semiconductor storage device, during a write operation, configures multiple bit lines so that bit lines that are adjacent to select bit lines are nonselect bit lines. The control circuit applies a first voltage to a write bit line that is included in the select bit lines, and also applies a second voltage that is higher than the first voltage, to a write inhibit bit line that is included in the select bit lines. Then, the control circuit applies a third voltage that is higher than the second voltage to the nonselect bit lines. As a result, the control circuit raises the voltage of the write inhibit bit line, while maintaining the write bit line at the first voltage. Next, the control circuit applies a fourth voltage for the write operation to the drain-side select gate line.