Non-volatile Semiconductor Storage Device Vertical Integration
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Solution Overview
Problem
Conventional semiconductor storage devices face challenges in reducing chip area and cost due to the complexity of lithography processes and the need for etching stoppers, which hinder further refinement and integration of memory cells.
Innovation Solution
A non-volatile semiconductor storage device with a memory string configuration featuring protruding layers and conductive layers that extend in a specific manner to reduce the need for large contact layers, allowing for easier polishing and integration, and a method of manufacturing that includes forming protruding layers and laminating conductive layers to cover them, thereby reducing the chip area occupied.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact layers are formed to reach laminated conductive layers in a stepwise manner, then connection between conductive layers is achieved, but chip area increases due to larger step widths required for etching stopper materials
Solution Approach 1:
The conductive layers are configured to extend in the vertical dimension (upward extension) rather than requiring larger horizontal step widths. This allows contact layers to reach the conductive layers without increasing the chip area, as the connection is achieved through vertical extension of the conductive layers themselves rather than through lateral expansion requiring etching stoppers
Solution Approach 2:
The invention removes the need for etching stopper materials by having the conductive layers extend upward to directly form the connection structure. This eliminates the additional film thickness of etching stopper materials that would otherwise be required, thereby removing the need for larger step widths and reducing the overall chip area
2Manufacturing precision
If lithography technology is improved to enable further refinement, then memory cell dimension is reduced, but manufacturing cost increases due to introduction of expensive EUV exposure devices
Solution Approach 1:
The invention transitions from two-dimensional planar integration to three-dimensional vertical integration by having conductive layers extend upward and memory cells arranged in multiple layers. This allows continued refinement of memory cell dimensions using existing lithography technology without requiring expensive EUV exposure devices, as the integration density improvement comes from the vertical dimension rather than further lateral refinement
3Productivity
If memory cells are arranged in a three-dimensional manner, then integration of memory devices is improved, but device complexity increases due to multiple laminated conductive layers and contact layers
Solution Approach 1:
The invention merges the functions of separate contact layers and extended conductive layers into a unified structure where the conductive layers themselves extend upward to form the connection. This reduces the number of distinct layers and manufacturing steps compared to conventional approaches that require separate contact layers deposited on top of stepwise conductive layers with etching stoppers
Solution Approach 2:
The invention removes the need for separate etching stopper material layers and reduces the number of contact layers required by having the conductive layers extend upward to directly provide the connection function. This simplifies the overall structure while maintaining the three-dimensional integration of memory devices
Data Source
AI summary
A non-volatile semiconductor storage device has a memory string including a plurality of electrically rewritable memory cells connected in series. The non-volatile semiconductor storage device also has a protruding layer formed to protrude upward with respect to a substrate. The memory string includes: a plurality of first conductive layers laminated on the substrate; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and an electric charge storage layer formed between the first conductive layers and the first semiconductor layer, and configured to be able to store electric charges. Each of the plurality of first conductive layers includes: a bottom portion extending in parallel to the substrate; and a side portion extending upward with respect to the substrate along the protruding layer at the bottom portion. The protruding layer has a width in a first direction parallel to the substrate that is less than or equal to its length in a lamination direction.