NOR Flash Memory Bit Line Coupling Noise Reduction
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Solution Overview
Problem
Conventional NOR-type flash memory devices suffer from program malfunctions due to adjacent cell bit lines being unintentionally programmed to high voltages caused by coupling noise during the application of a program voltage.
Innovation Solution
The NOR-type flash memory device includes a memory array with alternately defined first and second cell bit lines connected to respective sector bit lines through connection switches, a row selection circuit, a column selection circuit, and a program driver circuit, which controls the bit lines to prevent floating by applying a bias voltage to adjacent cell bit lines, thereby reducing or eliminating program malfunctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a program voltage is applied to a cell bit line for programming, then the programming function is achieved, but adjacent cell bit lines are unintentionally boosted to high voltages due to coupling noise causing program malfunctions
Solution Approach 1:
The patent introduces dummy bit lines as intermediary elements between adjacent cell bit lines. These dummy bit lines act as mediators that absorb or block the coupling noise from propagating to adjacent bit lines during programming operations, thereby preventing unintentional voltage boosting while maintaining the functionality of the memory device
Solution Approach 2:
The patent converts the harmful coupling noise effect into a beneficial by using it to identify which bit lines need dummy structures. By analyzing where coupling noise occurs during programming, the patent strategically places dummy bit lines only where needed, transforming the noise problem into a design criterion for improving programming reliability
2Ease of operation
If connection switches are used to connect cell bit lines to sector bit lines, then the memory array can be selectively accessed, but floating states in adjacent cell bit lines cause unintentional programming
Solution Approach 1:
The patent segments the bit line structure by dividing cell bit lines into groups that share common dummy bit lines. This segmentation allows the memory device to selectively activate specific dummy bit lines based on which cell bit lines are being programmed, providing precise control over program inhibition while maintaining selective access capability through the connection switches
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively controls adjacent cell bit lines to a ground voltage during programming, reducing or eliminating program malfunctions and ensuring reliable operation.
Implementation Method 1
A program voltage VPRO of about 5V may be applied to a cell bit line CBL<2> connected to the specific flash memory cell MC
Implementation Method 2
connection switches CNSW may be driven to connect respective bit lines CBL to their corresponding sector bit line TBL
Implementation Method 3
This configuration effectively controls adjacent cell bit lines to a ground voltage during programming
Data Source
AI summary
Embodiments of the present invention include a NOR-type flash memory device capable of reducing or eliminating program malfunctions. In some embodiments, the device includes a memory array, row selection circuit, column selection circuit, and program driver circuit. The memory array includes a memory sector having a first sector bit line and a second sector bit line. The memory array also includes a plurality of flash memory cells disposed on a matrix structure having a plurality of cell bit lines and a plurality of word lines arranged sequentially. The cell bit lines are alternately defined as first cell bit lines and second cell bit lines in sequential order. The first cell bit lines are connected to the first sector bit line in response to column selection signals thereof, and the second cell bit lines are connected to the second sector bit line in response to column selection signals thereof.