NOR Flash Cache Reads for Low-Latency Code Fetching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Code fetch latency from NOR flash memory in small computing devices is high due to the protocol-dependent nature of NOR flash controllers, which affects the performance of these devices, especially in IoT devices with limited memory and power resources.
Innovation Solution
Implementing a memory controller that distinguishes between legacy and continued-read commands based on the continuity of memory addresses, using a cache to store data when the continued-read command is used, thereby reducing latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data is read directly from NOR flash memory array, then data retrieval is possible, but code fetch latency is high
Solution Approach 1:
The patent embeds a cache memory structure within the NOR flash memory device itself, creating a nested architecture where the cache is integrated into the memory chip. This allows the cache to serve as an intermediate buffer between the flash array and external controllers, reducing latency for code fetch operations while maintaining the existing memory device footprint.
Solution Approach 2:
The cache memory pre-loads and stores frequently accessed code data from the NOR flash array before it is requested by the processor. By performing this preliminary data retrieval and storage action, the system eliminates the need for repeated high-latency reads from the flash memory array, thereby reducing overall code fetch latency.
2Use of energy by moving object
If data is read from NOR flash memory using traditional protocols, then data can be retrieved, but power consumption is high
Solution Approach 1:
The cache memory pre-loads code data during periods when the processor is not actively executing instructions, performing the energy-intensive data retrieval operation in advance. This preliminary action reduces the need for frequent, high-power reads from the NOR flash memory during critical code execution periods, thereby reducing overall power consumption while maintaining fast code fetch latency.
Solution Approach 2:
The patent creates a copy of frequently accessed code data in the cache memory, which consumes less power to access than the original NOR flash memory. This copying mechanism allows the processor to retrieve instructions from the lower-power cache rather than the higher-power flash memory, reducing overall system power consumption while maintaining fast access times.
Data Source
AI summary
A memory device may respond to two types of read commands. When the memory device receives a first type of read command, the memory device may read data from a memory array beginning at an address indicated in association with the received read command. When the memory device receives a second type of read command, the memory device may begin reading data from a cache in the memory device. Data that is read from the memory array may also be stored in the cache.