3D NOR Flash Memory Cell Density via Vertical Channel Pillars
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Solution Overview
Problem
The two-dimensional structure of NOR flash memory limits its cell density, making it less competitive with NAND flash in terms of storage capacity and high-speed read applications.
Innovation Solution
A three-dimensional memory device manufacturing method is developed, utilizing gate all around (GAA) transistor structures with patterned conductive and dielectric layers, charge storage layers, and channel pillars to increase cell density and achieve high read speeds, similar to NAND flash.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If NOR flash is formed as a two-dimensional structure, then read speed is improved, but cell density deteriorates
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional vertical structure by forming channel pillars that extend in the vertical direction (Z-axis) and wrapping gate electrodes around them. This dimensional change allows multiple memory cells to be stacked vertically, dramatically increasing cell density while preserving the parallel connection architecture that enables high read speeds characteristic of NOR flash
2Speed
If NOR flash uses parallel connection of memory cells, then read speed is improved, but cell density is limited
Solution Approach 1:
The patent resolves this contradiction by extending the parallel connection architecture into the vertical dimension. Multiple memory cells are stacked along the Z-axis, each maintaining parallel connections for high-speed reads, while the vertical stacking reduces the horizontal area occupied by each cell, thereby increasing overall cell density
3Quantity of substance
If three-dimensional structure is implemented, then cell density is improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is divided into discrete, manageable stages: forming sacrificial patterns, creating through-holes, depositing channel pillar materials, removing sacrificial layers, and forming gate electrodes. This segmentation of the complex 3D manufacturing process into sequential steps makes it more controllable and manufacturable
Solution Approach 2:
Sacrificial patterns are formed in advance before the actual memory cell structures are built. These preliminary sacrificial structures serve as templates that guide the formation of channel pillars and gates, simplifying the overall manufacturing process by providing a pre-established framework
Data Source
AI summary
A memory device and a manufacturing method are provided. The method includes: forming a first conductive pattern on a substrate; forming an active structure over the first conductive pattern, wherein the active structure comprises a gate pattern, a channel pillar and a charge storage layer, the channel pillar penetrates the gate pattern and electrically connects with the first conductive pattern, and the charge storage layer is disposed between the gate pattern and the channel pillar; forming a second conductive pattern over the active structure, wherein the second conductive pattern is electrically connected with the channel pillar; and performing formation of the active structure one more time, such that the channel pillars of the active structures are vertically spaced apart from each other, and electrically connected to the second conductive pattern extending in between the channel pillars.