NOR Flash Memory Cell Pairing for Capacitive Coupling
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Solution Overview
Problem
Current semiconductor memory devices, such as NOR flash memory, face limitations in design and fabrication processes that affect their performance and efficiency, particularly in the arrangement and capacitive coupling of memory cells, leading to suboptimal data storage and retrieval capabilities.
Innovation Solution
The proposed solution involves a semiconductor memory array with bit line diffusions and memory cells formed in pairs, featuring first and second conductors adjacent to the bit line diffusions, floating gates beside these conductors, an erase gate between the floating gates, and at least one additional conductor capacitively coupled to the floating gates, which enhances capacitive coupling and improves programming and erasing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are arranged in pairs with additional conductors capacitively coupled to floating gates, then programming and erasing efficiency is improved, but device complexity increases
Solution Approach 1:
The memory cell is divided into pairs with shared components (bit line diffusions, source line diffusions, erase gates) and individual floating gates. This segmentation allows efficient parallel operation while reducing redundant structures, improving programming and erasing efficiency without proportionally increasing complexity.
Solution Approach 2:
The additional conductors serve multiple functions: they act as coupling gates for capacitive coupling during programming, provide voltage control during erasing operations, and enable selective cell access. This multi-functionality improves operational efficiency while the shared structures between cell pairs help control complexity.
2Reliability
If additional conductors are added for capacitive coupling, then data storage capability is enhanced, but manufacturing complexity increases
Solution Approach 1:
Adjacent memory cells share common structures including bit line diffusions, source line diffusions, and erase gates. This merging reduces the total number of discrete components that need to be manufactured, enhancing data storage capability while mitigating manufacturing complexity through patterned fabrication processes.
Solution Approach 2:
The additional conductors act as intermediary coupling gates between control signals and floating gates. These mediators enable precise capacitive coupling for reliable data storage while their standardized placement and connection methods simplify the manufacturing process through repeatable fabrication steps.
3Area of stationary object
If cells are formed in pairs with shared structures, then area efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
Memory cells are organized in pairs with clearly defined shared and individual components. The shared bit line diffusions and source line diffusions are positioned at standardized intervals, creating modular units that improve area efficiency while allowing manufacturing processes to target specific regions with controlled precision requirements.
Solution Approach 2:
Different regions of the memory structure have differentiated requirements: shared structures (bit line diffusions, source line diffusions) require high precision for alignment and spacing, while individual floating gates have localized precision requirements. This local quality approach optimizes area efficiency while concentrating manufacturing precision efforts where most critical.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the capacitive coupling between conductors and floating gates, enabling efficient programming and erasing of memory cells, enhancing data storage and retrieval capabilities while minimizing overerase risks, thus overcoming the limitations of prior art.
Implementation Method 1
at least one additional conductor capacitively coupled to the floating gates
Data Source
AI summary
Semiconductor memory array and process of fabrication in which a plurality of bit line diffusions are formed in a substrate, and memory cells formed in pairs between the bit line diffusions, with each of the pairs of cells having first and second conductors adjacent to the bit line diffusions, floating gates beside the first and second conductors, an erase gate between the floating gates, and a source line diffusion in the substrate beneath the erase gate, and at least one additional conductor capacitively coupled to the floating gates. In some disclosed embodiments, the conductors adjacent to the bit line diffusions are word lines, and the additional conductors consist of either a pair of coupling gates which are coupled to respective ones of the floating gates or a single coupling gate which is coupled to both of the floating gates. In another embodiment, the conductors adjacent to the bit line diffusions are program lines, and the third conductors are word lines which extend in a direction perpendicular to the program lines and the diffusions.