NOR Flash Column Leak Prevention Circuit
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Solution Overview
Problem
NOR flash memory devices experience column leak currents due to memory cell transistors with threshold voltages near 0V, making it difficult to accurately read stored information, and existing solutions require high gate breakdown voltage transistors for column leak prevention.
Innovation Solution
The semiconductor memory device incorporates a column leak prevention circuit with first and second transistors having a gate breakdown voltage equal to or below the erase voltage, using a control line to apply voltages that prevent column leaks by keeping non-selected memory cell transistors disconnected from the ground line during read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high gate breakdown voltage transistors are used for column leak prevention, then column leak currents are prevented, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The column leak prevention function is segmented into two separate transistors (first transistor connected to source line, second transistor connected to bit line) rather than using a single high-breakdown-voltage transistor. Each transistor operates at lower voltage stress, dividing the protective function across multiple components with simpler requirements.
Solution Approach 2:
The first and second transistors act as intermediary protective elements between the memory cell transistors and the read/write circuits. These intermediary transistors control the connection to ground lines during read/write operations, preventing column leaks without requiring high breakdown voltage.
2Quantity of substance
If memory cell transistors with threshold voltage near 0V are used, then storage capacity is improved, but column leak currents increase making accurate reading difficult
Solution Approach 1:
The first and second transistors are activated in advance during read/write operations to preemptively block column leak currents before they can affect the reading process. By controlling the ground line connections through these transistors, the harmful leak currents are prevented from interfering with the low-threshold-voltage memory cell operations.
3Reliability
If control lines are used to manage first transistor gates, then column leak prevention is achieved, but circuit complexity increases
Solution Approach 1:
The control line connected to the first transistor gates serves multiple functions: it enables column leak prevention during read operations, facilitates write operations, and maintains circuit simplicity by using a shared control signal rather than separate control lines for each transistor. This multi-functional approach reduces overall circuit complexity.
Data Source
AI summary
A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix; a plurality of word lines commonly coupling the control gates of the plural memory cell transistors present in a identical first direction; a plurality of source lines commonly coupling the sources of the plural memory cell transistors present in the identical first direction; a plurality of bit lines commonly coupling the drains of the plural memory cell transistors present in a identical second direction intersecting the first direction; a first transistor having a drain coupled to the source line; a second transistor having a drain coupled to a source of the first transistor, a gate coupled to the word line and a source grounded; and a control line commonly coupling the gates of the plural first transistors.