NOR Flash Contact Hole Etching for Uniform Voltage Coupling
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Solution Overview
Problem
In NOR-type flash memory devices, the non-uniform structure of memory cells leads to incomplete erasure during erase operations, requiring multiple cycles and increasing operation time due to parasitic capacitance effects from misaligned contact plugs.
Innovation Solution
The method involves forming gate patterns with an etch stop layer on sidewalls to define a gap, followed by anisotropic and isotropic etching to create a contact hole that uniformly exposes the spacer patterns, ensuring consistent voltage coupling and reducing parasitic capacitance, thereby improving erasure efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional self-aligned contact formation is used, then contact hole alignment is achieved, but non-uniform voltage coupling causes incomplete erasure and increased operation time
Solution Approach 1:
The method performs preliminary etching to form contact holes with preliminary openings before final patterning. This preliminary action allows adjustment and optimization of voltage coupling uniformity across memory cells, ensuring complete erasure while maintaining alignment. The preliminary contact holes are formed with controlled dimensions that compensate for subsequent processing variations.
Solution Approach 2:
The invention changes the etching parameters by using anisotropic etching to create contact holes with specific width and depth characteristics. This parameter control ensures uniform voltage coupling to the floating gate, achieving consistent erasure performance across all memory cells in the array.
2Reliability
If multiple erase cycles are performed to ensure complete erasure, then erasure completeness is improved, but operation time increases
Solution Approach 1:
The contact structure is preliminarily formed with optimized dimensions and positioning before memory cell operation. This preliminary structuring ensures uniform voltage coupling that enables complete erasure in fewer cycles, reducing the time loss associated with multiple erase operations.
Solution Approach 2:
The invention replaces iterative erase operations with a structurally optimized contact system that achieves complete erasure in fewer cycles. By substituting process iteration with structural optimization, the total erase time is reduced while maintaining reliability.
3Manufacturing precision
If contact hole width is reduced to improve alignment, then manufacturing precision is improved, but etching selectivity and control become more difficult
Solution Approach 1:
The method introduces an intermediary etching process with controlled selectivity to form contact holes. This intermediary step uses specific etch recipes and conditions that provide sufficient control over contact hole dimensions while achieving the required alignment precision. The intermediary process acts as a bridge between rough alignment and fine precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the uniformity of voltage coupling across memory cells, reducing the likelihood of incomplete erasure and shortening erase operation times by minimizing the impact of misalignment in the photoresist pattern during contact hole formation.
Implementation Method 1
The interlayer dielectric layer is anisotropically etched to form a preliminary contact hole that has a width that is narrower than the width of the gap
Implementation Method 2
At least one sidewall of the preliminary contact hole is isotropically etched to form a contact hole
Data Source
AI summary
Methods of forming a cell of a NOR-type flash memory device are provided in which a first gate pattern having a first sidewall and a second gate pattern having a second sidewall that opposes the first sidewall are formed on a semiconductor substrate. A source/drain region is formed in the semiconductor substrate between the first and second gate patterns. An etch stop layer is formed on the first and second sidewalls that defines a gap region. A dielectric layer is formed in the gap region, and is then etched to form a contact hole. Finally, a conductive material is deposited in the contact hole.