NOR Flash DRAM Bus Transport Layer Pin Reduction
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Solution Overview
Problem
Current memory architectures that combine non-volatile and volatile memories, such as NAND-type flash with DRAM, face challenges in realizing the full advantages of both due to increased power consumption, pin count, and complexity, especially when integrating NOR-type flash memory with DRAM, as they require multiple ports and additional pins, leading to higher costs and complexity.
Innovation Solution
A memory architecture where a NOR-type flash memory array receives dynamic protocol commands from a DRAM controller using the DRAM protocol as a transport layer, allowing data to be written to the NOR-type flash memory array without disrupting DRAM operations, by channeling flash-specific commands through a shared digital bus interface and using a common dynamic bus for both NOR-type flash and DRAM arrays, reducing the number of pins and reusing circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If NOR-type flash memory array is integrated with DRAM using separate ports and pins, then both memory types can operate independently, but pin count increases and device complexity increases
Solution Approach 1:
The DRAM controller is designed to handle both DRAM operations and NOR flash operations through a single shared bus interface. The controller can dynamically switch between DRAM protocols and flash-specific command sequences, allowing one piece of hardware to perform multiple functions that would traditionally require separate dedicated controllers and pin sets.
Solution Approach 2:
The patent merges the DRAM bus interface and NOR flash interface into a single shared digital bus. The data buffer and address register are共用 by both memory types, and the control signals are multiplexed to serve both DRAM and flash operations, reducing the overall pin count and interconnect complexity.
2Reliability
If NOR-type flash memory array is integrated with DRAM using separate ports and pins, then both memory types can operate independently, but circuitry complexity increases
Solution Approach 1:
The DRAM controller is designed to handle both DRAM operations and NOR flash operations through a single shared bus interface. The controller can dynamically switch between DRAM protocols and flash-specific command sequences, allowing one piece of hardware to perform multiple functions that would traditionally require separate dedicated controllers and pin sets.
Solution Approach 2:
The patent merges the DRAM bus interface and NOR flash interface into a single shared digital bus. The data buffer and address register are共用 by both memory types, and the control signals are multiplexed to serve both DRAM and flash operations, reducing the overall pin count and interconnect complexity.
3Device complexity
If flash-specific commands are sent through shared bus, then pin count is reduced, but DRAM operation may be disrupted
Solution Approach 1:
The system dynamically switches between DRAM and flash operations based on the current command being executed. The shared bus is time-multiplexed between DRAM transactions and flash command sequences, with the controller intelligently scheduling access to ensure that flash programming operations do not interfere with ongoing DRAM reads or writes.
Solution Approach 2:
The flash programming process is segmented into distinct phases (command loading, data programming, completion status) that can be interleaved with DRAM operations. The controller divides the flash command sequence into smaller transactions that fit within the DRAM bus timing constraints, allowing both memory types to operate with minimal interference.
Data Source
AI summary
One embodiment of the present invention relates to a method for communicating NOR-type flash specific memory commands from a DRAM memory controller to a NOR-type flash memory array without disrupting DRAM operation. In this embodiment flash specific commands are channeled from the DRAM controller to the flash device by using the DRAM protocol as a transport layer. Data to be written to the NOR-type flash memory array are loaded into a data register and a sequence of programming commands are loaded into a mode register as a series of mode register write operations. Once the entire sequence of programming commands is loaded the NOR-type flash memory array the data in the data register is loaded into the NOR-type flash memory array. Other methods and circuits are also disclosed.