NOR Flash ECC Recovery for Boot Data Bit Error Drift
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Solution Overview
Problem
NOR flash memory faces challenges in maintaining high reliability due to increased bit errors in boot data, which are not adequately corrected by traditional ECC functions, especially when error counts exceed the ECC's correction capacity.
Innovation Solution
A NOR flash memory system with an ECC component for error checking and correcting, coupled with a recovery mechanism that identifies and corrects faulty memory cells by adjusting threshold voltages or verification voltages, and manages faulty cells to a redundant area, ensuring ECC functionality remains effective.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory capacity of NOR flash memory is increased through miniaturization, then the data capacity increases, but the probability of bit errors increases
Solution Approach 1:
The patent applies preliminary action by performing recovery operations on memory cells before errors accumulate beyond ECC correction capability. The system proactively identifies cells with threshold voltage drift through periodic reading and comparison against reference values, then applies recovery (programming or voltage adjustment) to prevent future bit errors. This anticipatory approach addresses the increased error probability from miniaturization before it compromises data integrity.
2Productivity
If boot data is read frequently from NOR flash memory, then system operation is enabled, but the probability of errors in boot data increases
Solution Approach 1:
The system performs preliminary recovery operations on memory cells storing boot data before errors can accumulate from frequent reading. By periodically monitoring threshold voltage drift in boot data regions and applying recovery proactively, the system maintains boot data integrity despite high read frequencies required for system operation.
Solution Approach 2:
The patent implements feedback mechanisms by continuously monitoring the state of memory cells through periodic reading and threshold voltage measurement. When drift is detected in cells containing boot data, the system triggers recovery operations. This closed-loop feedback ensures that frequent reading operations do not compromise boot data integrity, as the system responds to detected degradation with corrective action.
3Reliability
If traditional ECC function is used for error correction, then some bit errors are corrected, but errors exceeding ECC correction capacity remain uncorrected
Solution Approach 1:
The patent extends preliminary action beyond simple error detection to include proactive recovery that prevents errors from exceeding ECC correction capacity. By monitoring threshold voltage drift and applying recovery operations before errors accumulate, the system maintains an error margin that ensures ECC can always correct any remaining errors, thereby eliminating uncorrected errors entirely.
Solution Approach 2:
The system applies beforehand cushioning by creating a protective margin through recovery operations. By proactively correcting threshold voltage drift and reducing the error rate below ECC correction capacity, the system cushions against future errors that might otherwise exceed correction capability. This creates a safety buffer that guarantees error-free operation even under stress conditions.
Data Source
AI summary
A NOR flash memory suitable for protecting data requiring high reliability and an operation method thereof are provided. The NOR flash memory includes a memory cell array, including a plurality of memory cells; an ECC component for performing error checking and correcting on data read from the memory cell array; an error identification component for identifying an error pattern of a faulty memory cell for which error checking and correcting have been performed by the ECC component; and a recovery component for performing recovery on the faulty memory cell based on the identified error pattern to eliminate errors in the faulty memory cell.