Memory Emulation Mechanism for NOR Flash Wear Leveling
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Solution Overview
Problem
Microcontrollers with embedded non-volatile memory using NOR flash technology face inefficiencies in writing data, as setting bits from 0 to 1 requires a slow erase operation, whereas writing from 1 to 0 is fast, and existing solutions do not effectively emulate hardware erasable programmable read-only memory (EEPROM) operations efficiently.
Innovation Solution
A memory management system that translates virtual bus addresses to physical addresses in non-volatile memory, allowing for efficient writing by reallocating memory blocks when bits need to be flipped from 0 to 1, and using a master index for efficient page management and wear leveling to enhance endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If an erase operation is performed to change bits from 0 to 1 in NOR flash memory, then the bits can be set correctly, but the operation is slow and performed on blocks of bits
Solution Approach 1:
The memory space is segmented into multiple pages, with each page containing data and associated metadata (valid bit, allocation status). This segmentation allows the system to manage memory at a finer granularity, enabling selective operations on individual pages rather than entire blocks, thus improving write speed while maintaining manageable complexity through structured organization.
Solution Approach 2:
A memory management intermediary layer is introduced between the host and physical NOR flash memory. This intermediary handles the complexity of erase operations, allocation tracking, and wear leveling, translating simple write requests from the host into appropriate physical operations. This shields the host from complexity while enabling efficient write operations through intelligent intermediation.
2Productivity
If a page of NOR flash memory is programmed multiple times without erasing, then write operations are fast, but the individual bits can only be set from 0 to 1 by a slow erase operation
Solution Approach 1:
The system changes the parameter of bit representation by inverting the logical meaning: stored 0s represent logical 1s and stored 1s represent logical 0s. This parameter change allows the system to use fast program operations (writing 0s) to achieve what would traditionally require slow erase operations, thereby improving productivity while eliminating time loss for bit flipping.
Solution Approach 2:
The memory pages are pre-formatted with initialization patterns (all 1s or all 0s) during manufacturing or first allocation. This preliminary action establishes a known state that enables subsequent fast write operations without requiring erase cycles, as the pre-set state already accommodates the intended data pattern, thus improving write throughput while avoiding erase delays.
3Adaptability or versatility
If the system emulates EEPROM operations in NOR flash memory, then flexibility is improved, but the complexity of managing allocation and reallocation increases
Solution Approach 1:
The memory system implements self-service through automatic wear leveling and allocation management. The intermediary layer autonomously tracks page allocation status, performs wear distribution across memory blocks, and handles reallocation when pages become full or worn. This self-service capability provides EEPROM-like flexibility while containing complexity within the automated management layer, preventing complexity from propagating to the host system.
Data Source
AI summary
In an embodiment, a method comprises: obtaining a virtual bus address; translating the virtual bus address to a physical address of a portion of NVM storing first data; determining that the first portion of NVM has been allocated previously; reading the first data from the first portion of NVM; determining whether writing second data to the first portion of the NVM would change one or more bits in the first data; responsive to the determining that a write operation only changes data bits in the first data from 1 to 0, writing the second data over the first data stored in the first portion of NVM; and responsive to the determining that one or more bits in the first data would be flipped from 0 to 1, reallocating the first portion of NVM to a second portion of NVM, copying the first data from the first portion of NVM to the second portion of NVM with the first data modified by the second data.