NOR Flash Word-Line Erase Masking for Memory Reliability
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Solution Overview
Problem
Conventional NOR flash memory experiences accelerated deterioration and reduced reliability due to the inability to separately perform data erasing operations on fast or slow erase memory cells, leading to uneven erasing within memory blocks.
Innovation Solution
A method that involves performing a first block-type erasing operation followed by sequential erase verification, identifying failed word lines, and then conducting a second erasing operation on selected word lines while masking non-selected lines with a lower voltage to avoid repeated bias exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the entire memory block is erased in conventional operations, then the erasing operation can be performed uniformly, but the rapid deterioration of memory cells is accelerated and reliability is reduced
Solution Approach 1:
The memory block is divided into multiple word lines, and the erasing operation is segmented by word line rather than applying to the entire block uniformly. This allows different word lines to be erased independently based on their specific needs, preventing unnecessary erasure of already good memory cells while thoroughly erasing defective ones.
Solution Approach 2:
Different erasing strategies are applied to different word lines based on their local characteristics. Word lines with verification failures receive additional erasing operations, while word lines that pass verification are masked and protected from further erasure. This local differentiation resolves the contradiction between uniform operation and reliability.
2Manufacturing precision
If multiple erasing operations are performed on all word lines, then erasing completeness is improved, but memory cell degradation is accelerated
Solution Approach 1:
An erase verification operation is performed preliminarily after the first erasing operation to identify which word lines actually need additional erasing. This preliminary identification prevents unnecessary subsequent erasing operations on word lines that are already properly erased, thereby extending memory cell service life while ensuring erasing completeness for defective cells.
Solution Approach 2:
The erasing operation parameters are dynamically changed based on verification results. Word lines that pass verification have their erasing operations stopped (parameter change from active to inactive), while word lines that fail verification continue to receive erasing operations. This parameter adaptation ensures completeness without unnecessary degradation.
3Measurement precision
If sequential verification is performed on each word line, then erasing accuracy is improved, but the complexity of the erasing operation increases
Solution Approach 1:
The verification process is segmented by word line, with each word line verified independently. This segmentation allows the system to track the status of each word line separately and apply appropriate subsequent operations, achieving high verification accuracy without requiring complex centralized control mechanisms.
Data Source
AI summary
A memory device and a data erasing method are provided. The data erasing method includes: performing a first data erasing operation on a memory block, wherein the memory block includes a first word line to an Nth word line, and N is a positive integer greater than 1; performing an erase verification operation on the first word line to the Nth word line of the memory block one by one sequentially; finding a failed word line of a memory cell where a first verification failure occurs in the erase verification operation; and making the failed word line to the Nth word line at least one selected word line, making remaining word lines at least one non-selected word line, masking the at least one non-selected word line, and performing a second data erasing operation on a memory cell of the at least one selected word line.