NOR Flash Memory LTDR Testing via Dynamic Voltage Comparison
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Solution Overview
Problem
Current methods for testing low temperature data retention (LTDR) in NOR flash memory chips require lengthy idle periods, increasing research and development costs and product cycle times due to their time-dependent nature.
Innovation Solution
A semiconductor memory apparatus and testing method that includes a memory chip with a main and mini array, and a memory controller that detects initial and subsequent test voltages, dynamically updating comparison voltages based on idle time to assess whether specification requirements for LTDR are met in a shorter period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory chip is left idle for a long waiting time (more than 300 hours) to test LTDR specification requirements, then the reliability of the test result is improved, but the loss of time and productivity deteriorates
Solution Approach 1:
The patent applies preliminary action by performing an initial programming operation and initial read operation before the idle period to establish baseline voltage values. This preliminary setup enables the subsequent short-duration idle test (1-24 hours) to be sufficient for detecting LTDR failures, eliminating the need for traditional long idle periods (300+ hours) while maintaining test reliability
Solution Approach 2:
The patent changes the testing parameters by using dynamically updated comparison voltages that are adjusted based on the actual idle time elapsed. The memory controller updates comparison voltages at different time points (first comparison voltage after first idle time, second comparison voltage after second idle time), allowing accurate LTDR assessment within short timeframes rather than requiring fixed long-duration tests
2Measurement precision
If the memory chip is left idle for a long waiting time (more than 300 hours) to test LTDR specification requirements, then the accuracy of specification compliance determination is improved, but the productivity deteriorates
Solution Approach 1:
The patent implements feedback by continuously monitoring the read operation results during and after the idle period, and using this feedback to dynamically update comparison voltages. The memory controller adjusts the comparison voltages based on the actual voltage drift observed during the idle period, enabling accurate specification compliance determination within 1-24 hours instead of requiring 300+ hours for traditional methods
Solution Approach 2:
The patent applies dynamics by making the comparison voltage adaptive rather than static. The comparison voltage is dynamically updated based on the elapsed idle time and observed voltage characteristics. This dynamic adjustment allows the testing system to accurately determine specification compliance in a short time by adapting the reference values to the actual device behavior during the test period
Data Source
AI summary
A semiconductor memory apparatus and a testing method thereof are provided. The semiconductor memory apparatus includes a memory chip and a memory controller. The memory controller is configured to detect an initial test voltage of a target memory cell corresponding to a tailing bit in a main array of the memory chip. After the memory chip is idle for a first time, the memory controller detects a first test voltage of the target memory cell and compares it with a current comparison voltage to determine whether a first stage test is passed. In a case of passing the first stage test, after the memory chip is idle for a second time, the memory controller detects a second test voltage of the target memory cell and compares it with the current comparison voltage to determine whether a second stage test is passed. The comparison voltage is dynamically updated in response to the time the memory chip is idle.