NOR Flash Memory Data Set Validity Tagging
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Solution Overview
Problem
NOR flash memory technologies face inefficiencies in data storage and retrieval due to long erase and write times, which can lead to excessive wear and inefficient use of storage segments, as they require erasing entire blocks for updates.
Innovation Solution
Implementing a method where data is stored in NOR flash memory blocks by initializing them as 'fresh' with all locations set to a binary value, allowing subsequent data sets to be written without overwriting existing data by marking previous data as invalid through bit changes, thereby avoiding full block erasure and minimizing wear.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full block erasure is performed for data updates in NOR flash memory, then data integrity is maintained, but processing time increases and wear on memory increases
Solution Approach 1:
The patent divides the memory block into multiple segments with validity tags, allowing individual segments to be invalidated and updated independently rather than requiring full block erasure. This segmentation enables partial updates while maintaining data integrity through tag validation.
Solution Approach 2:
The patent pre-initializes memory blocks with validity tags set to indicate valid data. When updates are needed, only the tag is modified to invalidate specific segments beforehand, allowing immediate overwriting without full erasure. This preliminary tagging action prepares the memory for efficient incremental updates.
2Reliability
If full block erasure is performed for data updates in NOR flash memory, then data integrity is maintained, but memory wear increases
Solution Approach 1:
By segmenting the block into valid/invalid regions marked by tags, the patent enables updating only the necessary portions of memory. This reduces the frequency of full block erasures and program cycles, thereby minimizing wear on the flash memory cells and extending operational lifespan.
Solution Approach 2:
The patent applies partial action by invalidating and updating only the specific segments that contain changed data rather than erasing the entire block. This selective approach reduces the number of write/erase cycles on unaffected memory regions, preserving them and reducing overall wear.
3Loss of time
If incremental updates are implemented without full erasure, then processing time is reduced and wear is minimized, but storage segment efficiency decreases
Solution Approach 1:
The validity tags provide continuous feedback about the state of each memory segment. The system monitors tag states to determine which segments contain valid data and which can be overwritten, enabling intelligent allocation and updating strategies that optimize storage segment efficiency while maintaining fast incremental update capability.
Data Source
AI summary
An apparatus includes a solid-state a solid-state non-volatile computer memory; and a controller coupled to the memory. The controller to: generate a data set including a tag that indicates that the data set is valid; write the data set into a block of the memory, wherein the block includes multiple addressable locations set to a common first binary value before the write; generate a subsequent data set including a tag that indicates that the subsequent data set is valid; update the tag of the written data set to indicate that the written data set is invalid, wherein the update includes setting an addressable location corresponding to the tag to second binary value different from the first binary value; write the subsequent data set to addressable locations in the block of memory other than the addressable locations of the invalid data set.