NOR Flash Memory Parallel Programming Method
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Solution Overview
Problem
NOR flash memory devices have limited throughput due to time-consuming cell-by-cell programming methods, making them unsuitable for rapid data writing applications, while existing methods for NAND flash memory are not applicable to NOR devices.
Innovation Solution
A method for operating NOR flash memory devices that involves applying a once-bit-line operating method to select and concurrently program multiple memory cells, using single-junction-bias or double-junction-bias techniques to apply voltages to word lines and regions, allowing for simultaneous programming and erasing of memory cells in a NOR memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If cell-by-cell programming method is used in NOR flash memory device, then programming precision is maintained, but programming time increases and throughput is limited
Solution Approach 1:
The patent merges multiple cell programming operations into a single parallel operation by applying voltages to word lines and bit lines simultaneously. Multiple memory cells are programmed concurrently through shared word lines and bit lines, transforming sequential cell-by-cell programming into parallel batch programming, thereby increasing throughput while maintaining programming precision.
Solution Approach 2:
The patent segments the programming operation into voltage application phases and verification phases. By dividing the programming process into distinct stages with controlled voltage applications to different word lines and bit lines, the system can program multiple cells in parallel while maintaining precise control over each cell's programming state, thus preserving precision while improving throughput.
2Device complexity
If NOR flash memory device uses traditional programming method, then device simplicity is maintained, but programming time is excessive for data flash applications
Solution Approach 1:
The patent introduces dynamic voltage control mechanisms that adjust voltages on word lines and bit lines based on the programming stage and target cell states. By dynamically switching between different voltage levels and configurations, the system accelerates programming speed to meet data flash requirements while maintaining the relatively simple NOR flash device structure without requiring complex additional components.
3Productivity
If multiple memory cells are concurrently programmed, then throughput is enhanced, but voltage control complexity increases
Solution Approach 1:
The patent makes existing word lines and bit lines serve multiple functions: they are used for both addressing specific cells and for parallel programming of multiple cells. The same word lines and bit lines that provide cell selection capability are also utilized to apply programming voltages to multiple cells simultaneously, thereby increasing throughput without adding separate dedicated voltage control lines or structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces programming time and enhances throughput, making NOR flash memory devices suitable for data flash applications by enabling rapid data writing and erasing of multiple memory cells simultaneously.
Implementation Method 1
electrons or holes are injected into the doped polysilicon floating gate or the charge trapping layer via the channel hot electron effect or the channel hot hole effect to alter the threshold voltage
Implementation Method 2
a NAND flash memory device normally applies the positive Fowler-Nordehim electron tunneling or the negative Fowler-Nordehim electron tunneling
Data Source
AI summary
An operating method of a memory array is provided. The operating method includes performing a programming operation. The programming operation is performed by applying a first voltage to a bit line of the memory array and a second voltage to a plurality of word lines of the memory array to cause simultaneously programming a plurality of selected memory cells in the memory array.