3D NOR Flash Memory Vertical Channel Structure
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Solution Overview
Problem
The scaling-down of NOR flash memory cells leads to issues such as punch-through and the short channel effect, limiting the integrity and efficiency of memory cells.
Innovation Solution
A NOR-type flash memory is designed with three-dimensional memory cells, featuring memory transistors and select transistors with vertically extending channels, where one memory cell comprises one memory transistor and one select transistor, and the fabrication process involves forming conductive regions, insulating layers, and charge storage regions to enhance cell integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional scaling-down of memory cells is continued, then memory density increases, but punch-through and short channel effect occur leading to degraded memory cell integrity
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell layout to three-dimensional vertical channel structure. The channel extends in the vertical direction (depth dimension) rather than only in the plane, allowing memory cells to maintain integrity while achieving higher density through vertical stacking and three-dimensional active regions.
2Length of moving object
If gate length is decreased to increase memory density, then memory cell size reduces, but short channel effect deteriorates memory cell performance
Solution Approach 1:
The invention introduces vertical channel extension as a third dimension, allowing the channel to lengthen in the depth direction while the gate length in the planar view remains short. This three-dimensional channel structure mitigates short channel effects by providing effective channel length control through vertical geometry rather than relying solely on reduced planar dimensions.
3Area of moving object
If gate width is decreased to increase memory density, then memory cell area reduces, but punch-through effect increases reducing memory integrity
Solution Approach 1:
The patent employs three-dimensional active regions that extend vertically, allowing the channel to achieve sufficient effective width and length for preventing punch-through through vertical geometry. The channel connects source and drain regions in the depth direction, providing adequate charge control and preventing punch-through effects even when planar dimensions are reduced for higher density.
Data Source
AI summary
NOR flash memory that includes three-dimensional memory cells is provided. In the NOR flash memory of the present disclosure, one memory cell includes one memory transistor and one selection transistor. A common source 5 is formed over a silicon substrate 9, and an active region 3 extending in a vertical direction to electrically connect to the common source 5 is formed. A control gate 4 of the memory transistor and a selection gate line 2 of the selection transistor are formed to surround a side portion of the active region 3, and a top portion of the active region 3 is electrically connected to a bit line 1.