NOR Flash Erase Phase Segmentation for Host Timeout Prevention
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Solution Overview
Problem
NOR flash memory operations often exceed the time limits set by hosts, leading to potential data damage and system timeouts due to incomplete operations, making it unsuitable for memory cards that require rapid responses.
Innovation Solution
Divide erase operations into phases, allowing each phase to be completed within the host's specified time limit, with the controller sending ready signals after each phase to prevent timeouts and store phase information temporarily on the flash memory for resumption upon power-up.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If NOR flash memory is used for memory cards, then cost-effectiveness is improved, but operation time exceeds host time limits causing timeouts and data damage
Solution Approach 1:
The patent divides the flash memory erase operation into multiple phases (e.g., suspend and resume phases). Each phase can be completed within the host's time limit, allowing the host to receive ready signals and prevent timeouts. The operation is segmented such that phase one erases a first portion of memory blocks and phase two erases a second portion, resolving the contradiction between using cost-effective NOR flash and ensuring reliable operation completion within host time limits.
2Device complexity
If NOR flash memory operations are performed without phase division, then device complexity is reduced, but operation time exceeds host specifications causing system timeouts
Solution Approach 1:
The erase operation is segmented into multiple phases with intermediate ready signals. This segmentation allows the system to maintain relatively simple device architecture while ensuring each phase completes within host time limits, preventing timeouts and data damage.
Solution Approach 2:
The patent implements periodic action by inserting ready signals between erase phases. The host receives periodic status updates indicating when memory blocks are erased, allowing the host to maintain power and continue the operation without timeout. This periodic communication resolves the time loss issue while keeping the overall operation structure manageable.
3Reliability
If erase operations are divided into phases, then operation completion within time limits is improved, but device complexity increases due to phase management requirements
Solution Approach 1:
The patent segments the erase operation into phases managed by the flash memory device itself, with the controller automatically handling phase transitions. This segmentation improves reliability by ensuring each phase completes within time limits while minimizing the complexity burden on the host through automated phase management.
Solution Approach 2:
The flash memory device performs self-service by automatically managing the phase division and transitions without requiring complex host intervention. The device controller handles the segmentation logic, ready signal generation, and phase coordination internally, reducing the complexity burden on the overall system while ensuring reliable operation completion.
Data Source
AI summary
A flash memory that could not have completed an operation within a time required by a host may be able to work with the host by dividing the operation into phases that may be completed within the allocated time. As a result, a type of memory that would otherwise be unable to be implemented in a format, such as a memory card, may be used effectively.