NOR Flash Memory Power-Up Read Leakage Prevention

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Solution Overview

Problem

Conventional NOR flash memory systems experience leakage current from bit lines during erase operations, leading to read errors and requiring significant waiting time for post-program completion before reading can proceed.

Innovation Solution

A recover and read method that applies a negative voltage to un-selected word lines during the power-up reading operation, allowing normal operation without immediate post-program completion and preventing leakage current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the NOR flash memory performs erase operation without completing post-program operation, then operation speed is improved, but leakage current from bit lines occurs causing read errors

Engineering Contradiction:
Improveoperation speedVSAvoidread accuracy
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies a negative voltage to un-selected word lines before and during the read operation to prevent leakage current from affecting the read accuracy. This preliminary protective action counteracts the potential harmful effect of incomplete post-program operation, allowing the system to maintain both speed and reliability.

Inventive Principle:
Principle #9Preliminary anti-action

2Reliability

If the system waits for post-program operation completion before reading, then read accuracy is maintained, but significant waiting time is required

Engineering Contradiction:
Improveread accuracyVSAvoidwaiting time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs a read operation immediately after power-up without waiting for the post-program operation to complete. By applying negative voltage to un-selected word lines in advance, the system prepares the memory block to prevent leakage current effects, enabling early read access and reducing waiting time while maintaining read accuracy.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If negative voltage is applied to un-selected word lines, then leakage current is prevented, but additional voltage control complexity is introduced

Engineering Contradiction:
Improveprevention of leakage currentVSAvoidvoltage control complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The memory controller automatically applies negative voltage to un-selected word lines during the power-up reading operation without requiring external intervention or complex additional control circuits. The existing word line control mechanism is utilized to provide the negative voltage, allowing the system to maintain reliability while minimizing additional complexity.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Prevents leakage current and read mistakes, enabling immediate access to memory arrays without waiting for post-program operations to finish, enhancing the efficiency of NOR flash memory systems.

Implementation Method 1

applying a negative voltage to a plurality of un-selected word lines for the power-up reading operation to operate normally

Methodology Applied
Scientific EffectElectric Field: Electric Field

Data Source

PatentUS11635913B2NOR flash memory apparatus and recover and read method thereof
Publication Date: 2023.04.25 WINBOND ELECTRONICS CORP
  • US11635913B2 patent drawing
  • US11635913B2 patent drawing
  • US11635913B2 patent drawing

AI summary

A NOR flash memory apparatus and a recover and read method for the NOR flash memory apparatus are described. The recover and read method includes: operating a power-up process on the NOR flash memory apparatus during a power-up time period; operating a power-up reading operation and reading a mark bit of a memory block of the flash memory apparatus during a reading time period after the power-up time period; and, applying a negative voltage to a plurality of un-selected word lines for the power-up reading operation to operate without leakage current from bit lines of the memory block being caused and therefore to operate normally without causing mistakes.