NOR Flash Row Decoder Circuit for Selective Sector Erasing
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Solution Overview
Problem
NOR flash memory architectures face inefficiencies in erasing large sectors, requiring temporary buffers and slow file management, whereas NAND architectures excel in quick data handling and flexible erasing granularity, but lack random access speed.
Innovation Solution
A row decoder circuit with a NOR architecture that enables selective erasing by managing pre-decoding signals P and L, maintaining one signal active and applying negative voltages to selected rows, while keeping unselected rows floating, thus achieving high granularity and quick erasing similar to NAND architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If NOR architecture is used for flash memory, then random access speed is maintained high, but erasing efficiency deteriorates requiring temporary buffers and slow file management
Solution Approach 1:
The memory matrix is divided into multiple sectors, each with its own pre-decoding circuit portion. This segmentation allows independent erasing of specific sectors without affecting others, enabling efficient erasing operations while maintaining NOR architecture's random access capabilities.
Solution Approach 2:
Pre-decoding circuit portions are introduced as intermediary components between the address input and the main row decoder. These pre-decoders generate selection signals that enable selective erasing of specific sectors, improving erasing efficiency without sacrificing the fast random access特性 of NOR architecture.
2Device complexity
If traditional NOR architecture erasing is used, then simplicity is maintained, but erasing granularity is poor requiring erasing of large sectors (at least 128 kB)
Solution Approach 1:
The memory is organized into multiple sectors with dedicated pre-decoding circuits for each sector. This segmentation enables fine-grained erasing control at the sector level (e.g., 16 kB granularity) while keeping the overall NOR architecture simple and maintaining ease of manufacture.
3Manufacturing precision
If NAND architecture is used, then erasing granularity is improved (16 kB or better), but random access speed deteriorates
Solution Approach 1:
The patent applies different functional characteristics to different parts of the memory system. The pre-decoding circuit portions provide fine-grained erasing control (NAND-like granularity) for specific sectors, while the main NOR architecture maintains fast random access speed. Each sector can be erased independently with high granularity without compromising overall access performance.
Data Source
AI summary
The invention relates to a row decoder circuit for non volatile memory devices of the electrically programmable and erasable type, for example of the Flash EEPROM type having a NOR architecture. The proposed row decoder circuit allows to carry out the erasing step very quickly, for example with a granularity emulating at least 16 kB and even overcoming by at least 2 kB Flash memories of the NAND type. The memory can thus maintain high performances in terms of random access speed but shows a high erasing speed typical of memory architectures of the NAND type.