NOR Flash Read Voltage Stabilization During Read-While-Write

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Solution Overview

Problem

NOR flash memory devices experience significant fluctuations in read voltage during read while write (RWW) operations, leading to performance deterioration due to the difference in write and read voltages, which is not effectively mitigated by reducing the array size.

Innovation Solution

Incorporating a write voltage generator that levels down the write voltage to match the read voltage level before switching to read operation, and using switches to apply the read voltage to banks, ensuring a stable voltage level across sectors, thereby reducing voltage fluctuations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If the array size is reduced to mitigate voltage fluctuation, then the voltage stability during RWW operation is improved, but the storage capacity and integration density deteriorate

Engineering Contradiction:
Improvevoltage stabilityVSAvoidstorage capacity
Core Design Contradiction:
Stability of the object's compositionVSQuantity of substance

Solution Approach 1:

The memory array is divided into multiple independent banks (e.g., Bank 0, Bank 1, Bank 2, Bank 3). During RWW operation, different banks can be accessed simultaneously - some banks perform read operations while others perform write operations. This segmentation allows the system to maintain larger total array size for storage capacity while individual banks experience reduced voltage fluctuation due to isolated operation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A voltage compensation circuit or buffer is introduced as an intermediary between the write operation and the read operation. This intermediary component absorbs or compensates for the voltage fluctuations generated during write operations, preventing them from affecting the read operations. The buffer acts as a mediator that isolates the read path from the disturbances caused by write path.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If the write voltage is increased to improve write speed, then the write operation performance is improved, but the read voltage fluctuation during RWW operation worsens

Engineering Contradiction:
Improvewrite speedVSAvoidread voltage stability
Core Design Contradiction:
SpeedVSStability of the object's composition

Solution Approach 1:

The system dynamically adjusts the write voltage level based on the operation mode. During RWW operations, the write voltage is controlled to be lowered to match the read voltage level, preventing excessive voltage fluctuations. The voltage generator can switch between different voltage levels depending on whether a full write operation or a compensated write operation is being performed, making the system adaptive to different operational requirements.

Inventive Principle:
Principle #15Dynamics

3Productivity

If the voltage switching between write and read modes is performed quickly to improve operation efficiency, then the overall throughput is improved, but the voltage fluctuation and performance deterioration worsen

Engineering Contradiction:
Improveoperation throughputVSAvoidoperation reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

Before switching from write operation to read operation, the system performs preliminary voltage adjustment to ensure the voltage level is appropriate for the upcoming read operation. The voltage generator proactively prepares the voltage level in advance, smoothing the transition and preventing abrupt voltage changes that would cause fluctuations. This preliminary preparation ensures reliable operation during the transition phase between different operation modes.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8125839B2Memory device and method reducing fluctuation of read voltage generated during read while write operation
Publication Date: 2012.02.28 SAMSUNG ELECTRONICS CO LTD
  • US8125839B2 patent drawing
  • US8125839B2 patent drawing
  • US8125839B2 patent drawing

AI summary

According to example embodiments, a semiconductor memory device may include a write voltage generator configured to generate a write voltage to perform the write operation to at least one of a plurality of banks where the write voltage generator generates the write voltage to have a voltage level of a read voltage before the write operation changes to a read operation. The semiconductor device may also include a read voltage generator configured to generate a read voltage to perform the read operation to at least one of the other plurality of banks and/or a plurality of switches configured to switch a voltage applied to at least one of the banks to one of the write voltage and the read voltage in response to a plurality of control signals.