NOR Flash Memory Multiple Programming With Selective Error Correction
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Solution Overview
Problem
Existing NOR Flash memory technologies face inefficiencies in programming operations, leading to high erase operation frequency and potential read errors due to multiple programming without proper error correction management.
Innovation Solution
A method and memory chip design that determines the operating state of a storage space based on write instructions, enabling or disabling the error correction mechanism accordingly to manage multiple programming states, thereby reducing erase operations and improving read accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple programming operations are performed on memory cells between two erase operations, then the number of erase operations is reduced, but read errors increase due to accumulation of programming disturbances
Solution Approach 1:
The patent applies local quality by differentiating error correction strategies based on the specific state of memory regions. The system identifies whether a memory region is in a normal state or a multiple-programmed state, and applies appropriate error correction codes (ECC) selectively. For multiple-programmed regions, stronger error correction is applied, while normal regions use standard correction, thus resolving the contradiction between reducing erase operations and maintaining read accuracy.
Solution Approach 2:
The patent changes the parameter of error correction strength based on the programming history of memory cells. By detecting the number of programming operations performed on a memory region and adjusting the error correction code accordingly, the system enables multiple programming operations while maintaining data integrity. This dynamic parameter adjustment resolves the contradiction by adapting the correction level to the actual risk of read errors.
2Reliability
If error correction mechanism is always enabled during read process, then read accuracy is improved, but system complexity and overhead increase
Solution Approach 1:
The patent implements a dynamic error correction mechanism that adjusts its operation based on real-time memory state detection. The system dynamically determines whether to apply error correction based on the programming history and current state of memory regions, rather than using a static always-on approach. This dynamic adaptation reduces unnecessary error correction operations while maintaining accuracy when needed, thus reducing system complexity overhead.
Solution Approach 2:
The patent extracts the error correction decision-making process from a universal always-on mechanism and creates a selective application system. By separating the error correction function and applying it only to specific memory regions that require it (those in multiple-programmed state), the system reduces overall complexity while maintaining necessary reliability. This extraction principle allows the system to avoid the overhead of universal error correction application.
3Reliability
If frequent erase operations are performed to maintain memory cell accuracy, then read accuracy is maintained, but productivity and wear resistance deteriorate
Solution Approach 1:
The patent applies preliminary action by detecting and identifying multiple-programmed memory regions before read operations occur. The system proactively marks and monitors memory regions that have undergone multiple programming operations, preparing error correction mechanisms in advance for these high-risk regions. This preliminary identification allows the system to extend the interval between erase operations while maintaining accuracy through targeted error correction.
Solution Approach 2:
The patent implements a feedback mechanism where the system continuously monitors the programming history and state of memory cells. Based on this feedback information, the system adjusts its error correction strategy and determines when erase operations are truly necessary. This feedback loop allows the system to maintain memory cell accuracy without resorting to frequent erase operations, thus improving productivity and wear resistance.
Data Source
AI summary
This disclosure relates to a memory chip and an operating method thereof, which determines an operating state of a storage space corresponding to a write instruction, the operating state including an error correction protection state and a multiple programmed state and being represented by, for example, flag bits and error correction bits, and enables, in a later reading process, an error correction mechanism for the storage space in the error correction protection state, or disables the error correction mechanism for the storage space in the multiple programmed state. In this way, the storage space in the multiple programmed state may be recognized, allowing performing multiple programming operations thereon.