Tag-Based NOR Flash Data Capture with Loopback Clock Synchronization
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Solution Overview
Problem
The challenge lies in efficiently retrieving boot code data from nonvolatile serial NOR flash memory for System on a Chip (SoC) applications, where high-speed data capture is hindered by the small data window and timing delays introduced by physical interfaces, making it difficult to achieve rapid system boot times.
Innovation Solution
A loopback clock mechanism and tag-based implementation are introduced to synchronize clock domains, enabling uninterrupted data reads from non-contiguous memory areas and transparent pre-fetching, which increases interface operating frequency and reduces interconnect latency, thereby enhancing data capture efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional data retrieval methods are used from NOR flash, then the system can maintain simplicity in clock synchronization, but the data capture speed is limited by the small data window and timing delays
Solution Approach 1:
A feedback clock signal is introduced as an intermediary between the controller clock and the flash memory interface. The feedback clock is generated by passing the controller clock through the I/O socket, creating a synchronized clock that accounts for interface delays and allows high-speed data capture without complex synchronization logic
Solution Approach 2:
The patent implements a feedback mechanism where the clock signal is routed back through the I/O interface to create a feedback clock signal. This feedback loop allows the system to automatically compensate for timing delays and establish synchronized clock domains between the controller and flash memory, enabling high-speed operation
2Productivity
If the interface operating frequency is increased to reduce boot time, then the system boot speed improves, but the impact of interconnect latency and timing delays increases
Solution Approach 1:
The feedback clock signal is prepared in advance by routing it through the I/O socket before data transmission begins. This preliminary action establishes the correct timing relationships and synchronizes clock domains beforehand, allowing the system to operate at high frequencies without suffering from interconnect latency during actual data transfer
Solution Approach 2:
The feedback clock acts as a mediator that bridges the timing gap between the controller and flash memory interfaces. By creating a synchronized clock domain that accounts for interface delays, it enables high-speed operation while compensating for interconnect latency
3Adaptability or versatility
If data is read from non-contiguous memory areas, then the system can access scattered boot code segments, but uninterrupted data reads cannot be maintained
Solution Approach 1:
The patent implements dynamic tag-based control that allows the system to adaptively switch between contiguous and non-contiguous read modes. Tags indicate whether upcoming data is contiguous or non-contiguous, enabling the system to maintain uninterrupted reads when possible and efficiently handle non-contiguous accesses when required, optimizing both flexibility and efficiency
Data Source
AI summary
Embodiments disclosed herein generally relate for efficiently retrieving boot code for a processor from serial NOR flash memory. When a boot code request is received, a request handler in data capture logic tags successive address read requests to indicate whether the requests indicate contiguous addresses in the NOR flash memory for the boot code. Different circuitry in the data capture logic operates on different mesochronous clock signals. One clock signal drives the capture of boot code from NOR flash, and the other controls synchronized tagging, storing, pre-fetching, and transmitting of the captured boot code data.