Stacked NOR Flash TFT Strings With Vertical Gates for Fast Reads
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Solution Overview
Problem
Existing high-density memory structures, such as NAND and 3D NAND strings, suffer from high series resistance, limited TFT count, long latency, and susceptibility to program-disturb and read-disturb conditions, while NOR strings formed from conventional transistors are not well-established.
Innovation Solution
Organize multi-gate NOR flash thin-film transistor (TFT) strings as stacks of horizontal active strips with vertical control gates, allowing parallel connection of transistors and reducing activation of non-targeted TFTs during read/write operations, using charge-storage elements between active strips and control gates to minimize disturbance and enhance storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND memory strings with series-connected TFTs are used, then storage density is improved, but read latency increases and program-disturb/read-disturb conditions occur
Solution Approach 1:
The patent inverts the conventional NAND string architecture by switching from series connection to parallel connection of TFTs. This inversion fundamentally changes the current flow path, allowing read operations to access stored data without requiring activation of multiple TFTs in sequence, thereby dramatically reducing read latency while maintaining high storage density through the parallel architecture.
Solution Approach 2:
The patent segments the memory structure into multiple independent parallel TFT strings, each with its own control gates. This segmentation allows selective activation of individual strings during read operations, enabling fast access to specific data locations without disturbing or requiring activation of other strings, thus reducing read latency and preventing read-disturb conditions.
2Ease of manufacture
If polysilicon thin-film TFTs are used, then manufacturing simplicity is improved, but channel mobility decreases and series resistance increases
Solution Approach 1:
The patent changes the physical parameters of the TFT channel by reducing channel length and optimizing channel width in the parallel architecture. These parameter changes compensate for the inherently lower mobility of polysilicon thin-film TFTs, reducing the impact of high series resistance while maintaining the manufacturing simplicity of using deposited thin-films rather than single-crystal substrates.
3Loss of time
If NOR string architecture with parallel-connected TFTs is implemented, then read latency is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent implements multi-functional control gates that can operate in different modes (select gate, control gate, or both simultaneously) depending on the operation required. This universality allows the same physical structure to support both the simplified parallel NOR architecture for fast reads and the more complex NAND architecture for high-density storage, thereby reducing manufacturing complexity while maintaining low read latency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces read-latency, minimizes disturbance effects, lowers power dissipation, and decreases costs, achieving storage densities comparable to DRAM with lower cost-per-bit and improved reliability.
Implementation Method 1
Data storage in the TFTs of an active strip is provided by charge-storage elements provided between the active strip and the control gates provided by the adjacent local word-lines
Implementation Method 2
vertical local word-lines provided along one or both sidewalls of the stack of active strips
Data Source
Figure 1a~2a
Figure 1b
Figure 1c
AI summary
Multi-gate NOR flash thin-film transistor (TFT) string arrays ("multi-gate NOR string arrays") are organized as stacks of horizontal active strips running parallel to the surface of a silicon substrate, with the TFTs in each stack being controlled by vertical local word-lines provided along one or both sidewalls of the stack of active strips. Each active strip includes at least a channel layer formed between two shared source or drain layers. Data storage in the TFTs of an active strip is provided by charge-storage elements provided between the active strip and the control gates provided by the adjacent local word-lines. Each active strip may provide TFTs that belong to one or two NOR strings, depending on whether one or both sides of the active strip are used.