NOR Flash Memory Trench Structure for Leakage Suppression
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Solution Overview
Problem
Conventional NOR flash memories face issues such as increased leakage current between bit line and source line in non-selected cells during reading and writing, and the inability to reduce the gate length below 45 nm, hindering high-speed access and integration with NAND flash memories.
Innovation Solution
A NOR flash memory design incorporating a charge storage layer with an oxide-nitride-oxide (ONO) structure and a self-aligned trench formation process, reducing capacitive coupling and leakage current, and enabling compatibility with NAND flash memory manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a floating gate structure is used in conventional NOR flash memory, then charge retention characteristics are improved, but leakage current between bit line and source line in non-selected cells increases
Solution Approach 1:
The memory cell is divided into two functional parts: a surface transistor for charge storage and a sidewall transistor for leakage control. The sidewall transistor is formed in a trench structure alongside the active region, creating a separate control path that isolates the floating gate from the bit line, thereby reducing leakage current while preserving charge retention.
Solution Approach 2:
The solution transitions from a planar two-dimensional cell structure to a three-dimensional structure by forming a trench along the sidewall of the active region. This vertical dimension allows the sidewall transistor to be positioned above the bit line, creating an additional spatial separation that reduces capacitive coupling and leakage current without affecting the surface transistor's charge storage function.
2Area of moving object
If gate length is reduced below 45 nm for miniaturization, then cell area is reduced, but manufacturing precision becomes difficult to control
Solution Approach 1:
The trench structure is formed through self-aligned etching processes where the sidewall of the active region serves as its own alignment reference. The sidewall transistor's gate electrode is automatically positioned relative to the active region boundary, eliminating the need for additional alignment steps and reducing manufacturing variability in the effective gate length.
Solution Approach 2:
The trench is formed before the final gate electrode patterning, establishing a pre-defined geometric reference that guides subsequent processing steps. This preliminary structure ensures that the effective gate length is determined by well-controlled etch depths and widths rather than by precise lithographic patterning of the final gate.
3Adaptability or versatility
If NOR flash memory with high-speed access and NAND flash memory with large storage capacity are integrated on the same chip, then functionality is improved, but compatibility of cell array structures and manufacturing processes becomes difficult
Solution Approach 1:
The cell array structure uses a universal design where multiple memory cells are connected in series between bit line side select transistors and source line side select transistors, with word lines commonly connected to gates of memory cells in a row. This architecture is compatible with both NOR and NAND flash memory manufacturing processes, allowing integration of high-speed NOR cells and high-capacity NAND cells on the same chip using the same fabrication流程.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution suppresses leakage current and allows for high integration and miniaturization of NOR flash memory cells, enhancing compatibility with NAND flash memory structures.
Implementation Method 1
a charge storage layer, formed on the active region corresponding to each memory cell and including a nitride layer sandwiched between insulating layers
Implementation Method 2
suppresses leakage current of a non-selected cell and is compatible with a NAND flash memory
Implementation Method 3
a trench, adjacent to the active region
Data Source
AI summary
A NOR flash memory that suppresses leakage current of non-selected cells and is compatible with a NAND flash memory is provided. The NOR flash memory includes an active region, formed within a silicon substrate extending along a bit line direction; a trench, adjacent to the active region; a charge storage layer, formed on the active region corresponding to each memory cell; a sidewall insulator, formed within the trench and formed on a sidewall of the active region; a first conductive layer, formed on the charge storage layer for each memory cell; a first conductive layer formed on the charge storage layer corresponding to each memory cell; and a second conductive layer, formed on the first conductive layer extending along a word line direction. The second conductive layer is electrically connected to the first conductive layer and contacts the sidewall insulator within the trench.