NOR Flash Memory Vertical Electrode Integration
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Solution Overview
Problem
The challenge in reducing the size of flash memory cells while maintaining integration and reducing the process margin in non-volatile memory devices, such as EEPROM type flash memory, is difficult due to the complexity of forming contacts between floating gates.
Innovation Solution
A NOR flash memory device is fabricated using a semiconductor substrate with first polysilicon patterns, dielectric films, and second polysilicon patterns, where electrodes are formed in a columnar shape between adjacent polysilicon patterns, allowing for self-aligned ion implantation and reduced contact margin, enabling higher integration and compactness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the cell size is reduced to achieve higher integration, then the memory device becomes more compact, but it becomes difficult to secure process margin and prevent etching damage
Solution Approach 1:
The patent transitions from a planar contact structure to a three-dimensional vertical structure by forming electrode lines extending downward into the substrate and providing contacts at their lower ends. This vertical arrangement allows horizontal polysilicon patterns to be placed closer together while maintaining adequate contact spacing, thus reducing cell area while preserving process margin.
Solution Approach 2:
The patent introduces dielectric films as intermediary structures between the polysilicon patterns and substrate. These dielectric layers provide physical separation and protection, enabling tighter spacing of conductive elements while preventing direct contact that would cause short circuits or etching damage, thereby allowing smaller cell size with maintained manufacturing precision.
2Ease of manufacture
If contacts are formed between floating gates using conventional methods, then the memory device can be fabricated, but the process complexity increases and design margin is reduced
Solution Approach 1:
The patent segments the contact formation process into distinct vertical and horizontal components. Vertical electrode lines are formed first extending into the substrate, then horizontal polysilicon patterns are deposited on top. This segmentation allows each component to be optimized independently and simplifies the overall fabrication process compared to forming complex three-dimensional contacts between floating gates.
Solution Approach 2:
The patent performs preliminary formation of the vertical electrode lines and dielectric structures before depositing the polysilicon patterns. This preliminary action establishes a prepared substrate structure that guides subsequent processing steps, reducing the complexity of contact formation and eliminating the need for complex alignment and etching operations between floating gates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for higher integration and compactness of flash memory devices by minimizing the interval between polysilicon patterns, reducing the need for design margins, and preventing etching damage to electrodes, thereby enhancing the memory device's operational efficiency and speed.
Implementation Method 1
forming electrode lines on the semiconductor substrate between adjacent first polysilicon patterns by performing an ion implantation process on the semiconductor substrate using the first polysilicon patterns as a mask
Data Source
AI summary
Embodiments of a NOR flash memory and method for fabricating the same are provided. Bit lines can be formed as self-aligned source and drain regions between adjacent first polysilicon patterns. Contacts for the source and drain regions can be provided according to bit line instead of per cell. Word lines can be formed as second polysilicon patterns, which are used as control gates, and are provided perpendicular to the longitudinal axis of the bit lines. During formation of the second polysilicon patterns, a dielectric film and exposed regions of the first polysilicon patterns can be etched to form floating gates below the second polysilicon patterns.