3D NOR Flash Memory In-Memory Vector Matrix Multiplication
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Solution Overview
Problem
Current vector matrix multiplication (VMM) accelerators face challenges in implementing analog circuits for both positive and negative polarities and multi-bit resolution, particularly in deep neural network applications, where efficient in-memory computing is required.
Innovation Solution
A 3D AND-type NOR flash memory device is used to create a VMM accelerator, allowing for in-memory computing by directly sensing read currents from memory cells without the need for external arithmetic logic units, enabling high-capacity and high-speed operations through a signal processing circuit and differential analog-to-digital conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is read from memory to external ALU for computation, then computing can be performed using conventional digital logic, but data transfer time increases and system efficiency decreases
Solution Approach 1:
The patent merges the memory array with the computing function by implementing vector matrix multiplication directly within the memory device. The memory cells store weights and the read currents represent computational operations, combining storage and processing into a single integrated system that eliminates data transfer between separate memory and computing units.
Solution Approach 2:
The patent introduces a signal processing circuit as an intermediary between the memory array and external systems. This circuit performs analog-to-digital conversion and signal conditioning directly at the memory interface, enabling computational results to be processed and output without requiring data to be transferred to external arithmetic logic units.
2Measurement precision
If analog circuits are implemented for both positive and negative polarities in VMM, then multi-bit resolution computing can be achieved, but circuit complexity increases significantly
Solution Approach 1:
The patent segments the computing function into multiple independent memory cell sets (first through fourth sets) organized in pairs. Each pair handles specific computational aspects, with differential signaling used to represent positive and negative values. This segmentation allows multi-bit resolution to be achieved through parallel simpler circuits rather than a single complex analog circuit.
Solution Approach 2:
The patent changes the parameter representation from direct analog voltage levels to differential current signals. By using differential read currents from paired memory cell sets, the system can represent multi-bit values with positive and negative polarities while maintaining circuit simplicity. The signal processing circuit converts these differential currents into digital values through analog-to-digital conversion.
3Productivity
If in-memory computing is implemented using 3D NOR flash memory, then high capacity and high speed computing is achieved, but the ability to handle both positive and negative inputs becomes challenging
Solution Approach 1:
The patent employs asymmetric organization of memory cell sets where the first and third sets are coupled to one global bit line while the second and fourth sets are coupled to another global bit line. This asymmetric coupling enables differential signaling that naturally represents positive and negative values, allowing the symmetric NOR flash memory technology to handle asymmetric computational requirements for signed arithmetic.
Solution Approach 2:
The patent adds a differential signaling dimension to the traditional single-bit memory cell operation. By organizing memory cells in pairs and using differential read currents, the system extends the computational capability from binary to multi-bit with signed arithmetic, effectively adding a polarity dimension to the computing operation without changing the fundamental memory cell structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient vector matrix multiplication and Cosine similarity computations within the memory device, reducing the need for data transfer and external processing, thereby achieving high-speed and low-power in-memory computing suitable for AI and big data applications like image processing and deep neural networks.
Implementation Method 1
Each of the plurality of first pairs of memory cells includes a first memory cell set coupled to a first global bit line and a second memory cell set coupled to a second global bit line
Data Source
AI summary
A memory device for CIM, applicable to a 3D AND-type flash memory, includes a memory array, input word line pairs, and a signal processing circuit. The memory array includes first and second pairs of memory cells. Each first pair of memory cells includes a first memory cell set coupled to a first GBL and a second memory cell set coupled to a second GBL. Each second pair of memory cells includes a third memory cell set coupled to the first GBL and a fourth memory cell set coupled to the second GBL. Each input word line pair includes a first input word line coupled to the first and the second memory cell sets, and a second input word line coupled to the third and the fourth memory cell sets s. The signal processing circuit is coupled to the first and second global bit lines.