NOR Flash Memory Voltage Sequences for Disturb Reduction
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Solution Overview
Problem
Existing methods for erasing, reading, and programming embedded NOR-type 2T PMOS flash memories face challenges such as erase, read, and program disturbs, which affect data integrity and reliability, requiring optimal operating conditions that consider chip production processes, circuit design, device characteristics, and cost factors.
Innovation Solution
A method for optimizing the operating conditions of NOR-type embedded 2T PMOS flash memories by specifying voltage configurations for erase, read, and program operations, including voltage ranges for N-type wells, control lines, and select gate lines, to ensure accurate data manipulation and minimize interference between sectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional erase operations are performed on flash memory sectors, then data in selected sectors is erased, but data in non-selected sectors is mistakenly changed (erase disturb)
Solution Approach 1:
The patent applies different voltage configurations to different regions (sectors) of the flash memory during erase operations. Selected sectors receive voltages that enable erase (e.g., Vpp on word lines, ground on bit lines), while non-selected sectors receive voltages that prevent erase conditions (e.g., Vcc on bit lines, inverted word line voltages). This localized voltage differentiation ensures that only intended sectors are erased while protecting others from disturb effects.
Solution Approach 2:
Before performing erase operations, the patent establishes protective voltage conditions on non-selected sectors in advance. By pre-configuring bit line voltages to Vcc and word line voltages to inverted levels (Vsl or Vss), the patent creates a protective state that prevents accidental erase conditions from developing, thereby counteracting potential erase disturb before it occurs.
2Measurement precision
If read operations are performed on flash memory cells, then data is read accurately, but power consumption increases and non-selected cells are disturbed (read disturb)
Solution Approach 1:
The patent divides the flash memory array into selected and non-selected regions, applying different voltage configurations to each. During read operations, only selected cells receive the full read voltage sequence (Vcc on bit lines, Vsl on source lines, appropriate word line voltages), while non-selected cells receive reduced or inverted voltages. This segmentation enables accurate reading of selected cells while minimizing power consumption and preventing read disturb in non-selected cells.
Solution Approach 2:
The patent dynamically changes voltage parameters (bit line voltage, source line voltage, word line voltage) based on the selection status of each cell. Selected cells receive voltage combinations that enable accurate threshold voltage measurement, while non-selected cells receive voltage combinations that keep them in a non-conductive state. This parameter differentiation achieves both read accuracy and low power consumption simultaneously.
3Manufacturing precision
If programming operations are performed on flash memory cells, then data is programmed accurately, but non-selected cells are mistakenly programmed (program disturb)
Solution Approach 1:
The patent implements location-specific voltage configurations during programming operations. Selected cells receive the programming voltage sequence (high voltage on control gates, appropriate bit line and source line voltages) necessary for accurate electron injection into the floating gate. Non-selected cells receive inverted or suppressed voltages (Vcc on bit lines, Vsl on source lines, inverted word line voltages) that prevent programming conditions. This localized voltage control ensures programming accuracy while eliminating program disturb effects on adjacent cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The optimized method effectively erases data without disturbing non-selected sectors, ensures accurate read operations with low power consumption, and prevents mistaken programming, thereby enhancing the reliability and competitiveness of embedded flash memory products.
Implementation Method 1
the erase operation generally utilizes the Fowler-Nordheim (FN) tunneling effect to discharge the electrons stored within the floating gate to increase the threshold voltage of the control gate transistor
Implementation Method 2
the program operation generally uses the band-band hot electron injection (BBHE) effect to inject electrons into the floating gate to lower the threshold voltage of the control gate transistor
Data Source
AI summary
The present invention relates to semiconductor technology, and provides methods for erasing, reading and programming a flash memory. In the present invention, when an erase operation is performed on the flash memory, for a sector selected for the erase operation, its N-type well is applied with a voltage of 8V˜12V, its bit line is applied with a voltage of 4V˜6V, and its word line is applied with a voltage of −7V˜−10V. When a read operation is performed on the flash memory, for a sector selected for the read operation, its N-type well is applied with a VCC voltage; for a flash memory cell selected for the read operation, its bit line is applied with the VCC voltage, and its source line is applied with a voltage of 0V. When a program operation is performed on the flash memory, for a flash memory cell selected for the program operation, its bit line is applied with a voltage of VCC−6.5V˜VCC−4.5V, and its bit line is applied with a voltage of VCC+6V˜VCC+9V. In full consideration of factors including the chip manufacturing process, chip circuit design, chip quality and cost, optimal operating conditions fit for erasing, reading and programming, a NOR-type embedded 2T PMOS flash memory are determined.