NOR Flash Word Line Charging via Dual-Stage Voltage Control
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Solution Overview
Problem
NOR architecture flash memory experiences delays in word line charging due to high resistance, which hinders quick voltage attainment and writing speed, especially when attempting to implement NAND specifications, leading to an enlarged memory area.
Innovation Solution
Applying an initial enable voltage higher than the target voltage for a pre-charge time to rapidly charge the word line, then switching to the target voltage, reducing the delay without increasing the memory area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a metal bypass and metallic contacts are added to rapidly charge the word line, then the word line delay is reduced, but the memory area is enlarged
Solution Approach 1:
The patent changes the voltage parameter by applying an initial enable voltage higher than the target voltage to the word line. This higher voltage accelerates the charging process, reducing the RC time constant effect without requiring additional physical structures like metal bypasses or contacts, thereby reducing word line delay without enlarging the memory area.
2Productivity
If the word line resistance is reduced to shorten charging time, then the writing speed is improved, but the device complexity increases
Solution Approach 1:
The patent changes the voltage parameter applied to the word line by using an initial enable voltage higher than the target voltage. This parameter change accelerates the charging process, improving writing speed without modifying the physical structure or adding complex components, thus avoiding increased device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method significantly reduces word line charging time and delay, enhancing writing speed without enlarging the memory area, thus addressing the limitations of conventional NOR architecture flash memory.
Implementation Method 1
This relative-large resistance increases the RC time constant of the word line so that the NOR architecture flash memory has a delay when selecting the word line
Data Source
AI summary
An operation method of a NOR architecture memory includes the following steps. First, a target word line is selected. Next, an initial enable voltage is applied to the target word line to charge the target word line. Then, the initial enable voltage is switched to a target voltage after a pre-charge time to make the target word line be charged to the target voltage. The initial enable voltage is higher than the target voltage. The pre-charge time corresponds to the initial enable voltage and the target voltage.