NOR Logic Gate Topology for Data-Independent Signal Delay
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Solution Overview
Problem
Conventional logic gates, such as CMOS NOR, OR, AND, and NAND gates, exhibit asymmetric pull-up/pull-down networks leading to varying output signal delays based on input data patterns, resulting in non-uniform signal transitions.
Innovation Solution
Designing logic gates with pull-up and pull-down networks that maintain uniform impedances independent of input data values, ensuring consistent logic signal delays across all input combinations by using a combination of PMOS and NMOS transistors in CMOS logic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional asymmetric pull-up/pull-down networks are used in CMOS logic gates, then the circuit structure is simple, but the output signal delay varies depending on input data patterns
Solution Approach 1:
The patent applies asymmetry by introducing different transistor configurations in the pull-up and pull-down networks. Specifically, it uses transmission gates with controlled switches to create asymmetric impedance paths that compensate for the inherent asymmetry in standard CMOS gates, achieving uniform delay for both rising and falling output transitions regardless of input patterns
Solution Approach 2:
The patent employs dynamic control of transistor switches within the pull-up and pull-down networks. The controlled switches adjust the impedance of each path dynamically based on the input data patterns, ensuring that the effective resistance remains balanced and produces uniform output delay across all operating conditions
2Loss of time
If uniform impedance pull-up/pull-down networks are implemented, then output signal delay becomes independent of input data, but the transistor configuration and circuit design become more complex
Solution Approach 1:
The patent segments the pull-up and pull-down networks into multiple controllable paths with individual switches. Each segment can be independently controlled to adjust its impedance, allowing the overall network to maintain uniform effective impedance across different input conditions while using manageable modular transistor configurations
Solution Approach 2:
The patent changes the impedance parameters of individual transistor paths dynamically through controlled switching. By adjusting which switches are on or off based on input patterns, the effective resistance of each pull-up and pull-down path is modified to maintain balance, reducing signal transition time disparity without requiring a complete redesign of the transistor configuration
Data Source
AI summary
Devices and methods are presented for supplying logic gate signals with a data-independent delay. The method provides a logic gate comprising a pull-up network connected to a pull-down network. The method supplies binary level digital data input signals to the pull-up network and pull-down network, which may be either single-ended or complementary. The pull-up network and pull-down network regulate current through the logic gate with a delay and impedance independent of the data signals. As a result, the logic gate supplies binary level digital logic output signals in response to the data input signals, with a uniform delay. For example, the logic gates may be one of the following: NOR gate, NAND gate, AND gate, or OR gate.