Floating-Gate NOR Memory Cell with Indium Implant Field Tuning

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Solution Overview

Problem

Existing nonvolatile semiconductor memory cells face inefficiencies in programming operations due to competing electric fields affecting electron direction, which can negatively impact read current and other operations.

Innovation Solution

Incorporating strategically placed indium implants throughout the substrate of the memory cell, combined with a specific architecture, to optimize programming efficiency while maintaining high read current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memory cell structure is adjusted to overcome competing electric fields and maintain optimal electron traveling direction during programming, then programming efficiency is improved, but threshold voltages of control gate are affected negatively which reduces read current

Engineering Contradiction:
Improveprogramming efficiencyVSAvoidread current
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces indium implants at specific locations (trench bottom, trench sidewall, and channel region) with different concentrations and depths to locally modify electric fields and threshold voltages. This localized doping approach allows optimization of electron injection efficiency at the floating gate interface while maintaining appropriate threshold voltages in the channel region for proper read current characteristics.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent modifies physical parameters including indium implant energy (50-150 keV), implant dose (1e14 to 1e16 atoms/cm²), and floating gate oxide thickness (50-150 nm) to optimize the balance between programming efficiency and read current. By adjusting these parameters, the electric field distribution and electron injection characteristics can be tuned independently from the threshold voltage characteristics.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If indium implants are added to improve programming efficiency, then device complexity increases, but manufacturing process becomes more challenging

Engineering Contradiction:
Improveprogramming efficiencyVSAvoiddevice structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The indium implantation process is segmented into multiple distinct steps: trench bottom implant, trench sidewall implant, and channel region implant. Each implant step targets a specific region with optimized parameters, allowing independent control of electric field modification in different areas. This segmentation enables complex functionality to be achieved through modular process steps rather than a single complex implant.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The indium implants enhance programming speed and efficiency, allowing the memory cell to reach a programmed state in 20 ns or less, with minimal impact on read current, ensuring high read current consistency regardless of the cell's programmed or erased state.

Implementation Method 1

The memory cell structure as described herein includes a plurality of indium implants that are strategically placed throughout the substrate of the memory cell

Methodology Applied
Scientific EffectIon Implantation: Ion Implantation

Data Source

PatentUS12603134B2NOR memory cell with floating gate
Publication Date: 2026.04.14 GREENLIANT IP LLC
  • US12603134B2 patent drawing
  • US12603134B2 patent drawing
  • US12603134B2 patent drawing

AI summary

An electrically erasable programmable nonvolatile memory cell includes a semiconductor substrate having a bit line region, a surface region apart from the bit line region in a lateral direction, and a trench region apart from the surface region in the lateral direction, the trench region comprising a bottom portion and a sidewall portion adjacent a trench in the semiconductor substrate; an electrically conductive control gate; an electrically conductive word line; and a floating gate insulated from the substrate and the word line and comprising: a first tip substantially aligned with the sidewall portion of the trench region of the substrate; and a second tip self-aligned with an edge of the word line that is farthest from the second portion of the control gate.