3D NOR Thin-Film Memory Strings With Segmented Etching Support
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Solution Overview
Problem
Existing methods for forming 3-dimensional NOR-type thin-film memory strings face challenges in achieving superior scaling while maintaining structural stability, often leading to issues like tilting, snaking, twisting, bowing, ribboning, or shorting between active strips, which require more silicon real estate and increase cost-per-bit.
Innovation Solution
The methods involve replacing a single high aspect ratio etch step with two or more etch steps of less challenging aspect ratios, using dielectric pillars for support, or employing multiple masking steps to form wider and more mechanically stable active strips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single high aspect ratio etch step is used to form active strips, then manufacturing process complexity is reduced, but structural stability deteriorates leading to tilting, snaking, twisting, bowing, and ribboning
Solution Approach 1:
The patent divides the single high aspect ratio etch step into multiple sequential etch steps with lower aspect ratios. Intermediate dielectric layers are deposited between etching steps to provide structural support. This segmentation reduces mechanical stress on active strips during fabrication, preventing deformation while maintaining manufacturing feasibility.
2Area of moving object
If narrower active strips are formed to achieve superior scaling, then memory density is improved, but structural stability worsens increasing susceptibility to tilting and ribboning
Solution Approach 1:
The patent introduces intermediate dielectric layers as intermediary structures between narrow active strips. These dielectric layers act as spacers and mechanical supports, preventing adjacent narrow strips from deforming or ribboning while maintaining the desired narrow width for high density. The dielectric material provides mechanical reinforcement without electrical interference.
3Length of stationary object
If taller active stacks with greater number of active layers are formed, then memory capacity is improved, but structural stability deteriorates causing tilting and snaking
Solution Approach 1:
The patent segments the formation of tall active stacks into multiple etching steps separated by dielectric layer deposition. After etching portions of the stack, intermediate dielectric layers are deposited to provide mechanical support before continuing etching. This prevents tall stacks from tilting or snaking by providing periodic structural reinforcement throughout the stack height.
4Strength
If more braces are placed at shorter intervals to enhance structural stability, then mechanical strength is improved, but silicon real estate increases raising cost-per-bit
Solution Approach 1:
The patent uses intermediate dielectric layers as space-efficient structural supports between active strips. These dielectric spacers provide mechanical reinforcement without requiring additional silicon real estate for braces. The dielectric material fills the space between strips, providing support while maintaining high density and low cost-per-bit.
Data Source
AI summary
Various methods overcome the limitations and achieve superior scaling by (i) replacing a single highly challenging high aspect ratio etch step with two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips, (ii) using dielectric pillars for support and to maintain structural stability during a high aspect ratio etch step and subsequent processing steps, or (iii) using multiple masking steps to provide two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips.