3D NOR Memory Staircase Structures for Layered Electrical Access
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Solution Overview
Problem
Existing 3-dimensional NOR-type memory structures face challenges in efficiently establishing electrical connections between multiple conductor layers, which is crucial for read, programming, and erase operations, due to the complexity of the multi-layered semiconductor and conductive structures.
Innovation Solution
The development of staircase structures within the memory array allows for efficient electrical connections by forming vias and buried contacts that access semiconductor or conductor layers, enabling connections to circuitry both above and below the memory structure without risking electrical shorts between active strips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional vertical connection methods are used in 3D memory structures, then electrical connections between multiple conductor layers can be established, but the complexity of the multi-layered semiconductor and conductive structures increases and electrical shorts between active strips may occur
Solution Approach 1:
The patent transitions from traditional vertical via connections to a staircase-like structure that extends horizontally across multiple conductor layers. This dimensional change allows electrical connections to be established by progressing step-by-step through adjacent layers rather than penetrating vertically through all layers, thereby reducing structural complexity and eliminating short-circuit risks between active strips.
2Ease of operation
If staircase structures are formed to access semiconductor layers, then electrical access to multiple conductor layers is improved, but the fabrication process complexity increases
Solution Approach 1:
The staircase structure divides the connection path into discrete segments, where each step corresponds to a specific conductor layer. This segmentation allows for systematic fabrication where vias and contacts are formed layer-by-layer in a controlled sequence, improving electrical access while managing fabrication complexity through modular processing steps.
Solution Approach 2:
The staircase structure is built progressively during fabrication, with each step prepared in advance before the next layer is connected. This preliminary action approach allows for careful formation of vias and buried contacts at each stage, ensuring proper electrical access while maintaining fabrication control through staged processing.
3Reliability
If multiple vias and buried contacts are formed to connect conductor layers, then electrical connectivity is enhanced, but the risk of electrical shorts between active strips increases
Solution Approach 1:
The staircase structure introduces intermediate connection points at each conductor layer step, acting as mediators that progressively transfer electrical signals between layers. These intermediate steps are spatially separated from active strips, serving as buffer zones that enable electrical connectivity while preventing direct contact and potential shorts between adjacent active strips.
Data Source
AI summary
Various methods and various staircase structures formed out of the active strips of a memory structure (e.g., a memory array having a three-dimensional arrangement of NOR memory strings) above a semiconductor substrate allows efficient electrical connections to semiconductor layers within the active strips.