Dual Standby Bias Control in NOR Memory for Lower Standby Current

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Solution Overview

Problem

NOR memory devices face high standby current draw due to joint read and write bias systems, which is a challenge in low-power systems.

Innovation Solution

Implementing a memory system with separate read and write bias systems, allowing for dual standby modes, including a fast read standby mode and a read plus write standby mode, to reduce standby voltage generation and current draw.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a joint read and write bias system is used in NOR memory devices, then the device structure is simplified, but standby current draw increases

Engineering Contradiction:

Improvebias system structureVSAvoidstandby current draw

Core Design Contradiction:

Device complexityVSUse of energy by moving object

Solution Approach 1:

The patent divides the previously joint read and write bias system into separate read bias system and write bias system. This segmentation allows independent control of bias voltages for read and write operations, enabling the memory device to enter different standby modes (read standby or write standby) based on operation type, thereby reducing standby current draw while maintaining operational functionality.

Inventive Principle:

Principle #1Segmentation

2Use of energy by moving object

If separate read and write bias systems are implemented, then standby current draw is reduced, but device complexity increases

Engineering Contradiction:

Improvestandby current drawVSAvoidbias system structure

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent implements dynamic switching between different standby modes (read standby, write standby, and power-down mode) based on the type of operation anticipated. The bias systems can be dynamically configured to provide appropriate voltages for upcoming operations, allowing the device to optimize between power consumption and operational readiness based on real-time conditions.

Inventive Principle:

Principle #15Dynamics

3Use of energy by moving object

If the memory device enters a low-power standby mode, then power consumption is reduced, but wake-up time increases

Engineering Contradiction:

Improvepower consumptionVSAvoidwake-up time

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-charging bias voltages during standby mode based on the anticipated operation type. When a read operation is expected, the read bias system maintains readiness; when a write operation is expected, the write bias system prepares in advance. This preliminary preparation reduces the actual wake-up time when the operation is initiated, while still allowing the device to enter a lower power state compared to full active mode.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentEP4184510B1System and methods for dual standby modes in memory

Publication Date: 2026.04.15 EVERSPIN TECHNOLOGIES INC

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AI summary

The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.