NOR Memory Vertical Single Crystal Channel
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Solution Overview
Problem
The low integration level and high resistance of polycrystalline silicon in NOR-type memory devices limit their performance and application scenarios, particularly in terms of read and write speed and storage capacity.
Innovation Solution
A NOR-type memory device is designed with a vertical single crystal channel and a gate stack on a substrate, where the channel's side surface is a (100) or (110) crystal plane, and the body region includes a stress layer or insulation layer to enhance mobility and storage capacity, with additional features like a second gate conductor layer and storage functional layers to optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If polycrystalline silicon is used as channel material to increase integration density through vertical stacking, then device integration level is improved, but channel resistance increases and overall device performance deteriorates
Solution Approach 1:
The patent changes the crystal structure parameter of the channel material from polycrystalline to single crystal, which fundamentally alters the electrical properties. This parameter change reduces channel resistance while maintaining the vertical stacking architecture, thereby improving device performance without sacrificing integration density
Solution Approach 2:
The patent employs a composite structure combining single crystal channel material with specific crystal plane orientations ((100) or (110)) and integrates it with vertically stacked gate electrodes and insulating layers. This composite architecture achieves both high integration density and low channel resistance by combining the advantages of single crystal materials with optimized vertical device stacking
2Quantity of substance
If vertical stacking is implemented to increase integration density, then storage capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar device architecture to vertical three-dimensional stacking, adding the vertical dimension to device structure. Multiple gate electrodes and channel regions are stacked vertically to increase storage capacity per unit area while maintaining manufacturability through standardized vertical fabrication processes
Solution Approach 2:
The patent divides the device into multiple discrete vertical segments including separate gate electrodes, insulating layers, and channel regions that are stacked sequentially. This segmentation allows for modular manufacturing where each layer can be independently formed and controlled, simplifying the overall manufacturing process despite the increased vertical complexity
Data Source
AI summary
Provided are a NOR-type memory device, a manufacturing method, and an electronic device. The device includes: a plurality of gate stacks extending vertically on a substrate, wherein the gate stack includes a first gate conductor layer and a first filling layer; at least one device layer surrounding a periphery of the gate stack and extending along a sidewall of the gate stack; and a single-crystal vertical channel on a side of the device layer close to the gate stack and in contact with the first filling layer. At least one side surface of the gate stack in the vertical direction is a (100) or (110) crystal plane; and/or the body region includes a second filling layer or the body region includes a second gate conductor layer and a third filling layer, wherein at least one of first and third filling layers is a storage functional layer.