3D NOR Memory Array Vertical Stacking Integration Density
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Solution Overview
Problem
NOR memory integration density is lower compared to NAND memory due to differences in memory cell circuit structure, necessitating innovative designs to enhance memory cell packing efficiency.
Innovation Solution
A three-dimensional NOR memory array structure with vertically stacked memory transistors, where multiple memory transistors share a vertically extended columnar gate structure and source/drain layers, allowing for reduced footprint and increased integration density through shared bit and word lines, and isolation between adjacent columns to minimize leakage and crosstalk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If memory transistors are arranged in parallel in NOR memory structure, then circuit operation is simplified, but integration density is lower compared to NAND memory
Solution Approach 1:
The patent transitions from planar parallel arrangement to three-dimensional vertical stacking of memory transistors. Multiple memory transistors are stacked vertically along the same column, sharing common gate structures and source/drain regions, thereby occupying less footprint area while maintaining parallel circuit operations. This vertical dimensionality enables higher integration density without complicating the circuit architecture.
Solution Approach 2:
The patent merges multiple memory transistors into a single vertical stack that shares common structural elements including gate structures, source/drain contacts, and interconnect regions. This consolidation allows multiple memory cells to occupy the space of a single transistor in traditional NOR architecture, significantly improving integration density while preserving the simplicity of parallel NOR cell operations.
2Quantity of substance
If vertically stacked memory transistors share columnar gate structures and source/drain layers, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent designs universal shared structures including common gate structures, shared source/drain contacts, and shared interconnect regions that serve multiple memory transistors in the vertical stack. These multi-functional elements reduce the total number of individually fabricated components and align them along a common reference framework, thereby managing manufacturing precision requirements while achieving high integration density.
3Object-affected harmful factors
If isolation parts are added between adjacent columns, then leakage and crosstalk are reduced, but device area is increased
Solution Approach 1:
The patent introduces isolation structures selectively at specific locations between adjacent vertical stacks where leakage and crosstalk are most problematic. Rather than uniformly isolating all regions, the isolation parts are strategically placed to provide localized electrical isolation, thereby reducing harmful effects while minimizing the overall area penalty.
Data Source
AI summary
Disclosed are NOR memory array, NOR memory and electronic device. The NOR memory array comprises: multiple vertical memory groups arranged in n rows and m columns on a horizontal plane, one vertical memory group includes at least h vertically stacked memory transistors, where n, m, and h are natural numbers greater than 1, wherein, the memory transistors in one vertical memory group share a vertically extended columnar gate structure, part or all of columnar gate structures of vertical memory groups in a same row are connected to a same word line, part or all of memory transistors located at a same stack layer in vertical memory groups in a same column are connected to a same bit line, and an isolation part, for isolating active areas and bit lines of the memory transistors in the adjacent columns, is arranged between adjacent columns of the vertical memory groups.