Integrated NOR-NAND Flash Memory Layout With Shared Bit Lines
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Solution Overview
Problem
Integrating NOR and NAND flash memory cell arrays on a single chip is challenging due to their different array structures, leading to complex manufacturing processes.
Innovation Solution
A semiconductor device integrating a NOR memory cell array and a NAND memory cell array, with a common bit line connected to both arrays, separate sense circuits for each, and a compatible manufacturing process to simplify integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If NOR flash memory and NAND flash memory are integrated on one chip, then a flash memory having the advantages of each may be provided, but the manufacturing process may be very complicated
Solution Approach 1:
The memory device is divided into distinct NOR memory cell array regions and NAND memory cell array regions with separate bit lines, allowing each region to be optimized for its specific memory type while sharing common substrate and processing infrastructure
Solution Approach 2:
Common processing steps and structures (such as charge storage layer formation, gate electrode patterning, and substrate processing) are designed to be universally applicable to both NOR and NAND memory cell arrays, enabling single-wafer fabrication processes that handle both memory types
2Ease of manufacture
If the same array structure is used for both NOR and NAND flash memory, then manufacturing is simplified, but the ability to provide high-speed reading and large memory capacity is reduced
Solution Approach 1:
Different bit line configurations are implemented in different regions: NOR memory cells have individual bit lines for high-speed random access, while NAND memory cells share common bit lines for efficient series programming, allowing each region to have the optimal structure for its function
3Adaptability or versatility
If a common bit line is used for both NOR and NAND memory cell arrays, then device integration is improved, but the load on bit lines increases
Solution Approach 1:
The bit line structure is segmented into NOR-specific bit lines and NAND-specific bit lines that are physically separated, allowing independent optimization of signal integrity and drive requirements for each memory type while maintaining overall device integration
Data Source
AI summary
A semiconductor device formed by integrating a NOR memory cell array and a NAND memory cell array is provided. A flash memory includes a memory cell array, formed by integrating the NOR memory cell array and the NAND memory cell array; a word line, connected to each memory cell; and a bit line, commonly connected to the NOR memory cell array and the NAND memory cell array. The NOR memory cell array includes multiple memory cells connected in series between a bit line side select transistor and a source line side select transistor. Each of the memory cells includes a memory cell transistor and a sidewall transistor connected in parallel. The NAND memory cell array includes multiple memory cells connected in series between a bit line side select transistor and a source line side select transistor.