Dynamic NOR-OR Decoder for SRAM Local Clock Generation
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Solution Overview
Problem
Current SRAM designs are limited by their dependency on external clocks, which restrict their performance due to duty cycle and jitter issues, and they consume excessive power due to high sense amplifier capacitance and address bit latching, hindering efficient read and write operations.
Innovation Solution
The implementation of a decoder with a pre-charge circuit, dynamic NOR and OR nodes, and a word line inverter structure that generates a local clock independent of the external clock, along with a reduced-capacitance sense amplifier and dynamic NOR-OR x-decoder architecture to optimize SRAM performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If SRAM uses external clock synchronization, then timing control is simplified, but performance is limited by duty cycle and jitter constraints
Solution Approach 1:
The patent divides the clock control into two independent parts: external clock for timing synchronization and internal local clock for operation control. This segmentation allows the SRAM cell to operate independently from external clock constraints while maintaining timing coordination through the clock enable signal generated from external clock edges.
2Reliability
If SRAM uses high-capacitance sense amplifier, then signal detection capability is improved, but power consumption increases significantly
Solution Approach 1:
The patent implements dynamic capacitance control in the sense amplifier by using transistor switches that adjust the effective capacitance based on operational state. During read operations, the sense amplifier uses higher capacitance for reliable signal detection, while during write operations, the capacitance is reduced to minimize power consumption and prevent signal interference.
3Stability of the object's composition
If SRAM latches address bits, then address stability during operation is improved, but additional power consumption and timing delay are introduced
Solution Approach 1:
The patent replaces continuous address latching with periodic address sampling synchronized to local clock edges. Address bits are sampled and latched only at specific moments when the local clock transitions, maintaining address stability during operations while eliminating continuous latching power consumption and associated timing delays.
4Reliability
If SRAM completes read/write operations within external clock half-cycle, then clock synchronization is maintained, but operation speed is constrained by external clock frequency
Solution Approach 1:
The patent introduces a local clock as an intermediary between the external clock and the SRAM cell operations. The local clock, triggered by external clock edges, provides internal timing that is independent of external clock frequency and duty cycle, allowing operations to proceed at faster speeds while maintaining synchronization through the clock enable signal mechanism.
Data Source
AI summary
A decoder for decoding an address having a plurality of bits ranging from a first address bit a1 to a last address bit aN, each address bit being either true or false is provided that includes a pre-charge circuit adapted to pre-charge a dynamic NOR node and a dynamic OR node and then allow the pre-charged dynamic NOR node and pre-charged dynamic OR node to float; a plurality of switches coupled between the dynamic NOR node and ground, each switch corresponding uniquely to the address bits such that the switches range from a first switch corresponding to a1 to an nth switch corresponding to aN, wherein any switch corresponding to a true address bit is configured to turn on only if its corresponding address bit is false, and wherein any switch corresponding to a false address bit is configured to turn on only if its corresponding address bit is true.