NOR-RRAM Hybrid Memory Cell Array Write Control
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Solution Overview
Problem
Current semiconductor storage devices face challenges in achieving high integration levels and low power consumption, particularly when integrating NOR flash memory and RRAM technologies, as the size of RRAM memory cells is not competitive with NOR memory cells, leading to decreased cost performance with increased integration.
Innovation Solution
A semiconductor storage device is designed with a memory cell array that combines a RRAM structure and a NOR flash memory structure on a single substrate, utilizing global bit lines shared between both arrays and a read/write control unit that applies a set write voltage to selected memory cells, enabling efficient read/write operations while minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If RRAM memory cells are integrated to increase integration level, then memory capacity is improved, but cost performance deteriorates due to larger cell size compared to NOR memory cells
Solution Approach 1:
The patent combines RRAM and NOR flash memory structures into a single integrated memory device on one substrate. The memory cell array includes both RRAM memory cells and NOR flash memory cells, allowing the system to leverage the high density of RRAM while maintaining compatibility with existing NOR flash memory interfaces and operations, thereby improving cost performance through unified manufacturing processes
Solution Approach 2:
The patent creates a universal memory structure where a single memory device can operate in both RRAM and NOR flash memory modes. The memory cell array is designed to support both memory types with shared control circuits and interfaces, enabling the system to function as either or both memory types depending on operational requirements, thus improving versatility and cost efficiency
2Use of energy by moving object
If RRAM memory cells are used, then power consumption is reduced due to no erase operation requirement, but memory cell size increases compared to NOR memory cells
Solution Approach 1:
The patent merges RRAM and NOR flash memory structures into a single integrated device, allowing the system to utilize the low power consumption advantage of RRAM for frequently accessed data while maintaining the proven reliability of NOR flash memory for other operations, thereby achieving overall power efficiency without sacrificing storage density
3Ease of operation
If a pulse voltage is applied to RRAM to switch between HRS and LRS for data storage, then write operation simplicity is improved, but voltage control precision must be increased to ensure reliable state switching
Solution Approach 1:
The patent introduces a write control circuit that acts as an intermediary between the control logic and the RRAM memory cells. This circuit generates precisely controlled write voltages with appropriate pulse widths and amplitudes, ensuring reliable switching between HRS and LRS states. The write control circuit manages the complexity of voltage control, allowing simple write operations at the interface while maintaining precise voltage control internally
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves high integration levels and low power consumption by optimizing the write operation on RRAM through voltage application, reducing power consumption and enhancing the reliability of set write operations, thereby improving the overall performance of the semiconductor storage device.
Implementation Method 1
a selected global bit line of the global bit lines is charged, and the selected memory cell is charged by applying a voltage charging the selected global bit line
Implementation Method 2
a pulse voltage is applied to the resistive random access element, so that the resistive random access element is turned to be in a high resistance state (HRS) or a low resistance state (LRS) in a reversible and non-volatile manner to store data
Data Source
AI summary
A semiconductor storage device and its writing method are provided. A memory cell array is formed on a substrate, and the memory cell array has an NOR array with an NOR flash memory structure and a resistive random access array with a resistive random access memory (RRAM) structure. A read/write control unit charges a selected global bit line when a set write operation is performed on a selected memory cell of the resistive random access array, and a set write voltage is applied to the selected memory cell by applying a voltage charging the selected global bit line.