3D NOR Memory Strings With Pre-Charge for Low Read Latency
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Solution Overview
Problem
Existing high-density memory structures, such as NAND and NOR strings, face limitations in read-latency, program-disturb, and power dissipation, with NOR strings being susceptible to background leakage currents and requiring frequent data retention, while NAND strings have high series resistance and limited scalability.
Innovation Solution
The implementation of NOR memory strings with horizontal active strips and vertical local word lines, where TFTs are organized in parallel, allowing for pre-charging to reduce read-latency and increase data throughput, and the use of quasi-volatile TFTs with modified charge-storing elements for enhanced write/erase cycle endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NOR strings are used for high-density memory storage, then storage density is improved, but read-latency increases and background leakage currents worsen
Solution Approach 1:
The memory array is divided into multiple independently decodable blocks, where each block can be accessed and decoded separately. This segmentation allows parallel processing of different data blocks, reducing the overall read-latency while maintaining high storage density through the NOR string architecture.
Solution Approach 2:
Data is pre-charged to bit lines before the read operation is initiated. This preliminary action reduces the time required during the actual read process, effectively reducing read-latency while maintaining the high storage density of the NOR string structure.
2Quantity of substance
If NOR strings are used for high-density memory storage, then storage density is improved, but power dissipation increases due to background leakage currents
Solution Approach 1:
The harmful background leakage currents are extracted and isolated into dedicated leakage path structures that are separate from the main data storage and access paths. This allows the leakage currents to be contained and managed independently, reducing their impact on overall power dissipation while maintaining high storage density.
Solution Approach 2:
Leakage path structures act as intermediary elements between the NOR string memory cells and the external environment. These intermediaries provide controlled paths for leakage currents, preventing them from affecting the main data storage functionality and reducing overall power dissipation.
3Device complexity
If NAND strings are used for memory storage, then series resistance is reduced, but scalability is limited
Solution Approach 1:
The memory architecture transitions from planar two-dimensional arrangements to three-dimensional vertical stacking of memory blocks. This dimensional change allows for significantly improved scalability by utilizing the vertical dimension, enabling higher storage capacity without proportionally increasing the footprint area, while maintaining manageable series resistance through the NOR string parallel architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves reduced read-latency, lower power dissipation, and increased storage density, with the ability to read, write, or erase multiple TFTs concurrently, while minimizing the effects of leakage currents and extending the endurance of memory cells.
Implementation Method 1
each comprising a channel layer formed between two shared source or drain layers, and vertical side edges of each active strip are formed as NOR strings with control gates in vertical local word lines along one or both sidewalls of the active strips, with charge-storing elements between the control gates and the active strips
Implementation Method 2
The TFTs are organized as NOR strings, with horizontal active strips running parallel to the surface of a silicon substrate and control gates in vertical local word lines along one or both sidewalls of the active strips
Implementation Method 3
Capacitive-Coupled Non-Volatile Thin-Film Transistor Strings in Three Dimensional Arrays
Data Source
AI summary
A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.