NorFlash Virtualizing Circuitry for Multi-Master Access Conflict Resolution
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Solution Overview
Problem
Existing systems face difficulties in allowing multiple master processors to efficiently access external NorFlash memory, as they often require exclusive access and struggle with managing concurrent read and write operations effectively.
Innovation Solution
A system on a chip with NorFlash virtualizing circuitry that suspends program or erase operations to enable read access and resumes them, using queues and schedulers to manage requests from multiple master devices, ensuring each device can independently access the external NorFlash memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple master processors access external NorFlash memory simultaneously, then accessibility and utilization of NorFlash is improved, but access conflicts and operation interference occur
Solution Approach 1:
The patent introduces a NorFlash virtualizing circuit as an intermediary layer between multiple master processors and the external NorFlash memory. This circuit manages access requests from multiple masters, arbitrates conflicts, and coordinates read/write operations to prevent interference while maintaining simultaneous access capability. The virtualizing circuit acts as a mediator that resolves access conflicts without requiring exclusive master-slave relationships.
2Speed
If read operations are prioritized over write operations, then read speed and responsiveness are improved, but write operation completion time increases
Solution Approach 1:
The patent implements dynamic priority adjustment in the NorFlash virtualizing circuit. The circuit can dynamically change operation priorities based on system state, operation type, and timing requirements. Read operations can be prioritized when data access is critical, while write operations can be expedited when program completion is urgent. This dynamic scheduling resolves the contradiction by adapting priorities rather than maintaining fixed precedence.
Solution Approach 2:
The virtualizing circuit employs periodic polling and time-sliced access patterns where read and write operations are serviced in alternating periods. This allows the system to periodically switch between prioritizing reads and prioritizing writes, ensuring that neither operation type is permanently starved while maintaining overall system responsiveness and throughput.
3Adaptability or versatility
If program and erase operations are suspended for read access, then multi-master read capability is improved, but program and erase operation duration increases
Solution Approach 1:
The NorFlash virtualizing circuit performs preliminary assessment and preparation before suspending program or erase operations. It evaluates read request urgency, estimates suspension impact, and pre-coordinates with ongoing operations. This preliminary action minimizes unnecessary suspensions and reduces the overall duration by only pausing operations when absolutely necessary for read access, rather than preemptively suspending all program/erase operations.
Data Source
AI summary
A system on a chip allows external NorFlash memory sharing by multiple master devices. The system on a chip is configured to use an external NorFlash memory and includes a plurality of master devices and NorFlash virtualising circuity. The NorFlash virtualizing circuitry is configured to suspend a program operation or an erase operation being carried out on the external NorFlash memory, permit a read operation to be carried out on the NorFlash memory and then resume the suspended program operation or erase operation. Each master device of the plurality of master devices operates as a master to independently access the external NorFlash memory.