North Bridge Bus Cycle Trapping for Debugging
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Solution Overview
Problem
Conventional bus cycle trapping systems in computer systems are inefficient and costly due to the inability to detect all types of bus cycles, particularly AGP-to-Memory cycles, and require time-consuming checks of all write cycles for configuration verification.
Innovation Solution
A bus cycle trapping system that utilizes a north bridge with registers to store trapping parameters, allowing it to trap specific bus cycles and send activating signals for system management interrupts, enabling the CPU to enter a debugging mode for efficient trapping of all bus cycles, including AGP-to-Memory and CPU-to-PCI configuration cycles, without additional hardware tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If Logic Analyzer is used to trap bus cycles, then bus cycle detection capability is provided, but AGP-to-Memory cycles cannot be detected and system cost increases
Solution Approach 1:
The north bridge is designed to perform multiple functions: normal bus cycle routing and trapping/detecting bus cycles. By integrating the trapping function into the existing north bridge structure, the system achieves universal detection capability for all bus cycle types (CPU-to-PCI, AGP-to-Memory, etc.) without requiring separate specialized hardware tools for different bus cycle types.
2Measurement precision
If Logic Analyzer is used to trap bus cycles, then some bus cycles can be detected, but additional hardware tools are required and system cost increases
Solution Approach 1:
The trapping function is merged with the north bridge's existing bus cycle routing functionality. The north bridge integrates both the normal data path and the trapping logic within a single component, eliminating the need for separate external Logic Analyzer hardware and reducing overall system complexity.
Solution Approach 2:
The north bridge performs self-diagnosis and self-trapping of bus cycles by monitoring its own internal operations. The trapping logic is embedded within the north bridge itself, allowing it to autonomously detect and report bus cycles without requiring external monitoring hardware.
3Reliability
If Hardware ICE is used to verify CPU-to-PCI configuration cycles, then configuration verification is possible, but all write cycles must be checked making the process time consuming
Solution Approach 1:
The north bridge pre-configures trapping parameters and filters for identifying configuration write cycles before actual verification begins. By setting up the trapping criteria in advance, the system can immediately recognize and capture relevant configuration cycles without needing to examine every single write cycle, significantly reducing verification time.
Solution Approach 2:
The north bridge implements feedback mechanisms that allow it to learn from and adapt to the verification process. The trapping logic can be dynamically adjusted based on observed bus cycle patterns, enabling more efficient identification of configuration cycles versus regular data transfers.
Data Source
AI summary
A bus cycle trapping system includes at least one register, a north bridge, a south bridge and a central processing unit (CPU). The register is configured to store at least one trapping parameter. The north bridge traps a bus cycle matching the at least one trapping parameter while issuing an activating signal. The south bridge sends a system management interrupt message according to the activating signal. The CPU enters a system management mode according to the system management interrupt and executes a system management interrupt routine for doing a debugging test of the bus cycle matching the trapping parameter.