Northbridge RAID Accelerator Offloading CPU Load

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Solution Overview

Problem

Conventional RAID systems burden the central processing unit with most of the RAID write operations, leading to poor performance in computer systems due to the heavy loading and inefficient data handling.

Innovation Solution

Incorporating a RAID accelerator within the Northbridge, which performs RAID operations using RAID control commands stored in a register, and utilizing a shadow register to map and execute RAID control commands, thereby reducing the load on the central processing unit and optimizing bus bandwidth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the central processing unit handles most RAID write operations, then the system can perform RAID functions, but the central processing unit becomes overloaded and system performance deteriorates

Engineering Contradiction:

ImproveRAID operation throughputVSAvoidcentral processing unit loading

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts the RAID operation processing function from the central processing unit and relocates it to a dedicated RAID accelerator card. This separation allows the central processing unit to focus on computational tasks while the RAID accelerator handles disk array operations independently, resolving the contradiction between performing RAID functions and avoiding CPU overload

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a RAID accelerator card as an intermediary component between the central processing unit and the disk array. This mediator receives RAID control commands from the central processing unit, processes them through dedicated RAID logic, and coordinates data transfer operations, thereby reducing the processing burden on the central processing unit while maintaining system functionality

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If the central processing unit performs RAID operations sequentially, then data consistency is maintained, but bus bandwidth is inefficiently utilized and latency increases

Engineering Contradiction:

Improvedata consistencyVSAvoidbus bandwidth utilization

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The patent implements preliminary action by having the RAID accelerator read required data from the disk array before the central processing unit issues write commands. The accelerator prepares data in advance and buffers it, allowing the central processing unit to issue commands without waiting for sequential data retrieval, thereby improving bus bandwidth utilization while maintaining data consistency through coordinated control

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent enables continuous useful action by allowing the RAID accelerator to perform data reading, XOR operations, and buffer management concurrently with central processing unit operations. This parallel processing continues useful actions without interruption, improving bus bandwidth efficiency while the accelerator ensures data consistency through coordinated write-back operations

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS7805567B2Chipset and northbridge with raid access

Publication Date: 2010.09.28 VIA TECH INC

AI summary

A Northbridge providing RAID access is coupled among a central processing unit, a system memory, and a Southbridge. Furthermore, the Northbridge further couples to a RAID through a Southbridge. The Northbridge include a RAID accelerator for performing RAID operations according to RAID control commands which are stored in a register.