Multi-Channel Notch Filter Multiplication for Low Phase Delay
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Solution Overview
Problem
Delta-sigma modulators face challenges in trading off power consumption, bandwidth, and resolution, and struggle with reducing response time and inter-channel phase delay, particularly in power-line filtering applications, while also making simultaneous measurements difficult.
Innovation Solution
A successive approximation register (SAR) converter system is employed, which oversamples data at a higher rate than the intended output data rate, allows for flexible trade-offs between power, data rate, and resolution, and enables simultaneous multi-channel measurements with a single analog-to-digital converter (ADC), using digital integrators to generate filter coefficients and applying weighting functions to phase-align channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If delta-sigma modulators are used for high resolution analog-to-digital conversions, then measurement precision is improved, but response time increases and power consumption cannot be effectively reduced
Solution Approach 1:
The patent changes the fundamental operating parameters by using SAR converter architecture with oversampling instead of delta-sigma modulation. The oversampling ratio is adjusted to achieve the desired resolution while maintaining faster response times, effectively decoupling the trade-off between precision and speed that plagues delta-sigma modulators
2Object-affected harmful factors
If delta-sigma modulators integrate over a period of time to provide notch filtering, then noise rejection is improved, but inter-channel phase delay increases
Solution Approach 1:
The patent applies periodic oversampling at a controlled rate to achieve noise filtering through averaging, rather than using long integration periods. This periodic sampling approach provides notch filtering capability while maintaining synchronized timing across multiple channels, reducing inter-channel phase delay
3Device complexity
If multiple data channels are multiplexed into a single delta-sigma ADC, then device complexity is reduced, but simultaneous measurements become difficult and inter-channel phase delay increases
Solution Approach 1:
The patent implements preliminary timing synchronization by capturing multiple channels at precisely synchronized moments before any processing occurs. The SAR converter is controlled to sample all channels simultaneously at each oversampling cycle, establishing a common time reference that eliminates inter-channel phase delay while using a single multiplexed ADC
4Device complexity
If delta-sigma modulators are used to eliminate programmable gain amplifiers, then device complexity and cost are reduced, but flexibility in trading off power consumption, bandwidth and resolution is limited
Solution Approach 1:
The patent introduces dynamic configurability through the oversampling ratio control in the SAR converter architecture. By dynamically adjusting the oversampling ratio, the system can flexibly trade off between power consumption, bandwidth, and resolution according to application requirements, providing adaptability that fixed delta-sigma modulator architectures lack
Data Source
AI summary
A system for processing sample sequences, that may include an input, a sequence of coupled registers, including an accumulator register, and first circuitry that may be coupled to the accumulator register and to the input. The input may be configured to receive a first number of sample sequences having two or more samples. To process the first number of sample sequences, the first circuitry may be configured to generate a current effective sample corresponding to the sample for each sample in each sample sequence, write the current effective sample to the accumulator register, and shift the contents of each register into a successive register in the sequence of registers. After processing, each register of at least a subset of the sequence of registers may hold a respective final effective sample that may correspond to a different position in a processed sample sequence.