Multi-Channel Notch Filter Coefficients for Fast Phase-Coherent ADC
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Solution Overview
Problem
Delta-sigma modulators face challenges in trading off power consumption, bandwidth, and resolution, and struggle with reducing response time and inter-channel phase delay, particularly in power-line filtering applications, while also making simultaneous measurements difficult.
Innovation Solution
A successive approximation register (SAR) converter is used to generate filter coefficients and apply them to a data stream, allowing for higher oversampling rates, flexible power and resolution trade-offs, and simultaneous multi-channel measurements with a single ADC, enabling faster response and lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If delta-sigma modulators are used for high resolution analog-to-digital conversion, then measurement precision is improved, but response time increases and power consumption cannot be effectively reduced
Solution Approach 1:
The patent changes the fundamental operating parameters of the ADC system by switching from delta-sigma modulation to successive approximation registration. This parameter change enables simultaneous multi-channel measurements without the integration time constraints of delta-sigma modulators, thereby reducing response time while maintaining measurement precision through the SAR converter's binary search algorithm
2Object-affected harmful factors
If delta-sigma modulators are used for power-line filtering applications, then noise filtering is improved, but inter-channel phase delay increases
Solution Approach 1:
The patent applies preliminary filtering actions by implementing notch filters that are specifically designed to remove power line harmonics before the ADC conversion process. By pre-filtering the signals and using simultaneous sampling across multiple channels, the system eliminates power line noise interference while maintaining phase coherence between channels, avoiding the phase delay problems inherent in sequential delta-sigma conversion
3Device complexity
If a single delta-sigma ADC is used for multiple data channels, then device complexity is reduced, but measurement simultaneity deteriorates
Solution Approach 1:
The patent implements dynamic channel switching within the SAR ADC architecture, where the multiplexer rapidly switches between multiple input channels during the conversion process. This dynamic operation allows the single ADC to effectively perform simultaneous measurements by capturing data from all channels within the same integration period, maintaining measurement reliability while keeping device complexity low
Data Source
AI summary
Provided is a system for generating coefficient values. The system may include a base function generator and a series of accumulators including a leading and a last accumulator. In the series of accumulators, the data output of each accumulator, except the last, may be coupled to the data input of a successive adjacent accumulator. The base function generator may be configured to output, to the leading accumulator, a series of data values that may correspond to a base function that is a specified order derivative of a filter function. Each accumulator may be configured to: add a data value currently at its data input to a currently stored data value to produce an updated data value that may correspond to a respective value of a specified order integral of the base function; store the updated data value in the accumulator; and output the updated data value at its data output.