Notch Stop Pulsing Process for Plasma Etching
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Solution Overview
Problem
The silicon semiconductor industry faces issues with notching or undercutting during the etching of silicon layers, particularly when fluorinated gases are used, leading to unreliable micro electromechanical system (MEMS) devices and yield loss, as fluorinated gases are less effective on insulator layers, causing lateral etching and compromising device features.
Innovation Solution
A notch stop pulsing process (NSPP) is implemented in a plasma processing chamber, involving a main etch step and an overetch step with alternating power levels applied to the bottom electrode, using different process recipes to control lateral etching and prevent notching, allowing for precise etching of silicon layers without hardware changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fluorinated gases are used for etching silicon layer, then etching speed is improved, but lateral etching increases causing notching
Solution Approach 1:
The patent applies periodic action by implementing a pulsing etch process that alternates between high power and low power phases. During high power phases, fluorinated gases etch silicon rapidly; during low power phases, lateral etching is suppressed. This periodic modulation of power allows the system to achieve both fast vertical etching and controlled lateral etching, resolving the contradiction between etching speed and precision.
2Productivity
If high frequency plasma system is used, then etching efficiency is improved, but lateral etching control becomes more difficult
Solution Approach 1:
The patent applies dynamics by making the bottom electrode power variable rather than static. The system dynamically adjusts the bottom electrode power between high and low states during the etch process. This dynamic control allows high frequency plasma systems to maintain high etching efficiency while preventing excessive lateral etching, as the low power phases suppress lateral etching while high power phases enable rapid vertical etching.
3Productivity
If etching continues until insulator layer is reached, then complete silicon layer removal is achieved, but notching compromises device reliability
Solution Approach 1:
The patent applies feedback by using endpoint detection to monitor when the silicon layer has been sufficiently etched and the insulator layer is approached. The system provides feedback signals that trigger adjustments in the etch process parameters, such as reducing power or changing gas flow, to prevent excessive lateral etching near the insulator interface while ensuring complete silicon layer removal. This feedback mechanism maintains device reliability by preventing notching that would compromise structural integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The NSPP significantly reduces lateral etching, minimizing notching and enabling the continued use of high frequency plasma systems without sacrificing control, thereby reducing defective devices and providing financial benefits by maintaining etching efficiency and reliability.
Implementation Method 1
a plasma processing chamber, a method for etching a substrate
Implementation Method 2
fluorinated gases such as SF6, NF3, and CF4
Data Source
AI summary
A method for etching a substrate having a silicon layer in a plasma processing chamber having a bottom electrode on which the substrate is disposed on during etching. The method includes performing a main etch step. The method also includes terminating main etch step when a predefined etch depth of at least 70 percent of thickness into silicon layer is achieved. The method further includes performing an overetch step. The overetch step including a first process step and a second process step. First process step is performed using a first bottom power level applied to bottom electrode. Second process step is performed using a second bottom power level applied to bottom electrode that is lower than first bottom power level. First process and second process steps are alternately performed a plurality of times. The method yet also includes terminating overetch step after silicon layer is etched through.