Notched Fin Transistor Mitigating Channel Punch-Through
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Solution Overview
Problem
Current FinFET technology is susceptible to channel punch-through, leading to premature breakdown due to the depletion layers of the source and drain connecting through the substrate, even at equilibrium, resulting in increased punch-through current at low gate voltages.
Innovation Solution
The FinFET structure is modified by varying the width of the fin portion under the shallow trench isolation (STI) to include a narrowed portion and a buried portion, with notches or varying shapes etched using anisotropic wet etching, reducing the channel punch-through effect by controlling the fin width and shape.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the channel is formed from the bulk substrate with a uniform fin structure, then the manufacturing process is simple, but the device is susceptible to channel punch-through effect leading to premature breakdown
Solution Approach 1:
The fin structure is modified to have different widths at different locations: a first width at the top portion and a second width at the bottom portion. This local variation in geometry prevents channel punch-through at the bottom while maintaining structural integrity and simplifying manufacturing compared to completely complex alternative structures.
Solution Approach 2:
The fin is divided into distinct segments: a top portion with a first width and a bottom portion with a second width. This segmentation allows the structure to simultaneously achieve punch-through prevention at the bottom and maintain manufacturing simplicity through standardized top-section fabrication processes.
2Reliability
If the fin width is reduced to prevent channel punch-through, then the reliability improves, but the channel surface area decreases affecting transistor performance
Solution Approach 1:
The fin width is made location-dependent: narrower at the bottom to prevent punch-through and wider at the top to maintain sufficient channel surface area for good transistor performance. This local differentiation resolves the contradiction between reliability and performance.
Solution Approach 2:
Instead of uniformly reducing fin width in one dimension, the invention varies the width along the vertical dimension of the fin, creating a tapered or stepped profile that provides punch-through protection at the bottom while preserving channel area at the top.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the channel punch-through effect, enhancing the reliability and performance of FinFET devices by minimizing premature breakdown and improving control over transistor operations.
Implementation Method 1
notches or varying shapes etched using anisotropic wet etching
Data Source
AI summary
A transistor includes a notched fin covered under a shallow trench isolation layer. One or more notch may be used, the size of which may vary along a lateral direction of the fin. In some embodiments, The notch is formed using anisotropic wet etching that is selective according to silicon orientation. Example wet etchants are tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH).