Notched Gate Etching for Uniform Wafer Profile Control
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Solution Overview
Problem
The challenge in semiconductor integrated circuit (IC) fabrication is maintaining the uniformity of notched gate structure profiles across a wafer, as existing methods often result in etch rate differences and critical dimension biases between center and edge regions, leading to defects and reduced chip yield due to metal gate protrusion and shorting issues.
Innovation Solution
A method is introduced that involves applying different etchant concentrations to different regions of a wafer during the formation of notched gate structures, using a plasma processing chamber with adjustable etchant flow rates and RF power to ensure uniform etching across the wafer, thereby maintaining consistent gate stack dimensions and reducing metal gate protrusion risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a notched gate structure is formed to enlarge the distance between adjacent gate structures, then metal gate protrusion is mitigated, but etch rate differences and critical dimension biases occur between center and edge regions of the wafer
Solution Approach 1:
The patent applies different etchant concentrations to different regions of the wafer during the etching process. Specifically, the edge region receives a higher etchant concentration than the center region to compensate for the slower natural etching rate at the edges, thereby achieving uniform gate structure dimensions across the entire wafer while maintaining the notched profile that prevents metal gate protrusion
2Manufacturing precision
If uniform etching is applied across the entire wafer, then manufacturing consistency is maintained, but edge region defects occur due to inherent etch rate differences
Solution Approach 1:
The patent implements a spatially varying etchant concentration distribution where the etchant concentration is increased in the edge region compared to the center region. This local adjustment compensates for the naturally slower etching rate at wafer edges, enabling uniform gate structure formation across the entire wafer surface and preventing edge region defects while maintaining overall manufacturing consistency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively maintains uniformity of notched gate structure profiles, reduces effective gate stack dimensions, and enhances chip yield by minimizing metal gate protrusion and shorting issues, while being integratable with existing semiconductor fabrication processes.
Implementation Method 1
patterning the gate stack layer, thereby forming a first gate stack over the first channel region and a second gate stack over the second channel region; and laterally etching bottom portions of the first and second gate stacks by applying different etchant concentrations to the first and second regions simultaneously
Data Source
AI summary
A method includes providing a substrate having a channel region, forming a gate stack layer over the channel region, forming a patterned hard mask over the gate stack layer, etching a top portion of the gate stack layer through openings in the patterned hard mask with a first etchant, etching a middle portion and a bottom portion of the gate stack layer with a second etchant that includes a passivating gas. A gate stack is formed with a passivation layer deposited on sidewalls of the gate stack. The method also includes etching the gate stack with a third etchant, thereby removing a bottom portion of the passivation layer and recessing a bottom portion of the gate stack.